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71M6515H Energy Meter IC
DATA SHEET
MARCH 2008 GENERAL DESCRIPTION FEATURES
The 71M6515H is a high-accuracy analog front end (AFE) IC that provides measurements for fourquadrant 3-phase metering. The combination of a 21-bit sigma-delta A/D converter with a six-input analog front end, a thermally compensated high precision reference and a compute engine results in high accuracy and wide dynamic range. Patented Single-Converter TechnologyTM reduces cross talk and cost. This IC also provides RTC and battery backup for time-of-use (TOU) metering.
Battery
RTC COMPUTE ENGINE VOLTAGE REFERENCE RAM
UART, IRQZ
HOST PROCESSOR
SSI
CONTROL
DIO
High Accuracy * < 0.1% Wh accuracy over temperature and 2000:1 range * Exceeds IEC62053/ANSIC12.20 specifications. * Precision ultra-stable voltage reference (10PPM/C) * Single Converter TechnologyTM reduces cross talk and power consumption * Six sensor inputs--referenced to V3P3 * Compatible with CTs, resistive shunts and Rogowski Coil sensors * -90dB THD max. * Digital temperature compensation * Sag detection * Measures Wh, VARh, VAh, Vrms, Irms, V-to-V phase and load angle on each phase * Four-quadrant metering. * Four low-jitter pulse outputs from selectable measurements * Four pulse count registers * Selectable default status for pulse pins * Same calibration data for 46Hz to 64Hz line frequency * Broad CT phase compensation (7deg) Battery Backup * Protects accumulated data and powers real time clock during power supply outage * Compatible with Li-ion, NiCd, or super-capacitor * Battery backup current 2A typical at 25C External Data Interface * UART Control Interface, two selectable data rates * 8 general-purpose I/O pins with alarm capability * 5 or 10MHz selectable high speed synchronous serial output for DSP interface * IRQ output signal for alarms and end of measurement intervals. * Alarms on voltage sag, over-voltage, over-current Low System Cost * Power Consumption 30mW @ 3.3V typical * Real-time clock with temperature compensation * Built-in power fault detection * Single 32kHz crystal time base * Single-supply operation (3.3V) * 64-lead LQFP package
TERIDIAN 71M6515H
Figure 1: Meter block diagram
As shown in the block diagram (Figure 1), the host processor communicates with the 71M6515H through a UART interface using the programmable IRQZ interrupt. The 71M6515H calculates and accumulates meter measurements for each accumulation interval. A high-speed synchronous serial port (SSI) is provided to facilitate high-end metering. Integrated rectifying functions on the battery backup circuit enable minimal external component usage and minimum back-up current. Also, eight multi-purpose pins are provided for control of peripherals.
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CURRENT
VOLTAGE
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71M6515H Energy Meter IC
DATA SHEET
MARCH 2008
VREF IA VA IB VB IC VC
VX TEMP
PULSEW ADC CONVERTER
PULSER
V3P3A
GNDA
GNDA
GNDD VOLT REG 21 GNDD GNDD V2P5
2.5V to logic
MUX
V3P3A +
V3P3D
VREF
VREF
MUXSYNC
VBIAS (1.5V)
CALCULATIONS SSI INTERFACE OUTPUT VALUES: Whr (A, B, C) VARhr (A, B, C) VAhr (A, B, C) Vrms (A, B, C) Irms (A, B, C) Iphase (A, B, C) Frequency (Selected Phase) Temperature SSCLK SSDATA SFR SRDY
SYSTEM CLOCKS
CK_GEN
CKTEST
ALARMS: Voltage Sag (A, B, C) Zero Cross (Selected Phase) Over-Voltage (All) Over-Current (All) D0-D7 State Change BATTERY BACKUP OSC (32KHz) XIN XOUT
RTC VBAT PULSE4 PULSE3 PULSE_INIT BAUDRATE TX UART RX D0 D1 D2 D3 Change of State (D0...D7) I/O CONTROL D4 D5 D6 D7 DATA RAM
MISC
CONTROL
IRQZ
TEST VFLT FAULT DETECT VX RESERVED 64 PINS -- 64 TQFP RESETZ
March 3, 2008 VBIAS (1.5V) V3P3
GNDD TMUXOUT
Figure 2: IC Functional Block Diagram
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DATA SHEET
MARCH 2008 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Supplies and Ground Pins: V3P3D, V3P3A |V3P3D - V3P3A| VBAT GNDD Analog Output Pins: VREF V2P5 Analog Input Pins: IA, VA, IB, VB, IC, VC VFLT, VX XIN, XOUT Digital Input Pins: RX D0...D7 All other pins Operating junction temperature (peak, 100ms) Operating junction temperature (continuous) Storage temperature Solder temperature - 10 second duration ESD Stress Pins IA, VA, IB, VB, IC, VC, RX, TX All other pins -0.5V to 4.6V 0V to 0.5V -0.5V to 4.6V -0.5V to +0.5V -1mA to 1mA, -0.5V to V3P3A+0.5V -1mA to 1mA, -0.5 to 3.0V -0.5V to V3P3A+1.0V -0.5V to V3P3A+0.5V -0.5V to 3.0V -0.5V to 3.6V -0.5V to 6V -0.5V to V3P3D+0.5V 140 C 125 C -45 C to 165 C 250 C 6kV 2kV
Stresses beyond Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GNDA.
RECOMMENDED OPERATING CONDITIONS PARAMETER 3.3V Supply Voltage (V3P3A, V3P3D)+ VBAT
+
CONDITION Normal Operation Battery Backup No Battery Battery Backup
MIN
TYP
MAX
UNIT
Operating Temperature
3.0 3.3 3.6 V 0 3.8 V Externally Connect to V3P3D 2.0 3.8 V -40 85 C
V3P3A and V3P3D should be shorted together on the circuit board. GNDD and GNDA should also be shorted on the circuit board.
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MARCH 2008 LOGIC LEVELS PARAMETER Digital high-level input voltage, VIH Digital low-level input voltage, VIL ILOAD = 1mA Digital high-level output voltage VOH ILOAD = 15mA Digital low-level output voltage VOL Input pull-up current, IIL RESETZ E_RXTX, E_ISYNC/BRKRQ E_RST Other digital inputs Input pull down current, IIH TEST Other digital inputs ILOAD = 1mA ILOAD = 15mA VIN=0V CONDITION MIN 2 -0.3 V3P3D -0.4 V3P3D0.6 0 TYP MAX V3P3D 0.8 V3P3D UNIT V V V V 0.4 0.8 100 100 100 +1 100 +1 V V A A A A A A
10 10 10 -1 VIN=V3P3D 10 -1 SUPPLY CURRENT
PARAMETER V3P3A + V3P3D V3P3A current V3P3D current VBAT current VBAT current, VBAT=3.6V
CONDITION Normal Operation, V3P3A=V3P3D=3.3V VBAT=3.6V
MIN
TYP 8.8 3.7 5.1
MAX 11.5 4.7 6.8 300 4 12
UNIT mA mA mA nA A A
-300 Battery backup, 25C V3P3A=V3P3D=0V fOSC = 32kHz 85C VREF 2 4
PARAMETER VREF output voltage, VNOM(25) VREF output impedance VNOM definition A VREF(T) deviation from VNOM(T)
CONDITION
MIN
TYP
MAX
UNIT V k V
Ta = 25C 1.193 1.195 1.197 2.5 ILOAD = 10A, -10A 2 VNOM(T) = VREF(22) + (T-22)TC1 + (T-22) TC2
VREF(T ) - VNOM(T ) 10 6 Ta = -40C to +85C VNOM max(|T - 22 |,40)
VREF aging
-10
+10
PPM/C
25
PPM/year
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MARCH 2008 2.5V VOLTAGE REGULATOR PARAMETER Voltage Overhead V3P3D-V2P5 PSRR V2P5/V3P3D CONDITION Reduce V3P3 until V2P5 drops 200mV RESETZ=1, ILOAD=0 RTC PARAMETER Range for date RESETZ PARAMETER Reset pulse width Reset pulse fall time CRYSTAL OSCILLATOR PARAMETER Maximum Output Power to Crystal4 Xin to Xout Capacitance Capacitance to DGND Xin Xout Watchdog RTC_OK threshold CONDITION MIN TYP MAX 1 3 5 5 25 TEMPERATURE SENSOR PARAMETER Nominal Sensitivity (Sn) Nominal Offset (Nn) 4 Temperature Error
4
MIN
TYP
MAX 440
UNIT mV mV/V
-3
+3
CONDITION
MIN 2000
TYP --
MAX 2255
UNIT year
CONDITION
MIN 5
TYP
MAX 1
UNIT s s
UNIT W pF pF pF kHz
CONDITION TA=25C, TA=75C Nominal relationship: N(T)= Sn*T+Nn TA = -40C to +85C
MIN
TYP -900 40000 0
MAX
UNIT LSB/C LSB
ERR = (T - 25) -
( N (T ) - N (25)) Sn
-3
+3
C
PULSE GENERATOR TIMING SPECIFICATIONS PARAMETER PULSEW, PULSER maximum rate PULSE3, PULSE4 maximum rate Pulse count frequency CONDITION
31 APULSE=2 -1, 15 WRATE=2 -1 31 PULSE3=2 -1, WRATE=215-1
MIN
TYP
MAX 7.56 0.15 0.15
UNIT kHz kHz kHz
all pulse outputs
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MARCH 2008 THERMAL CHARACTERISTICS PARAMETER Thermal resistance, junction to ambient (RJA ) CONDITION Air velocity 0 m/s. Part soldered to PCB. VALUE 63.7 UNIT C/W
UART HOST INTERFACE PARAMETER Baud Rate Character set Data Format Byte-to-byte delay (6515H times out after maximum delay) Byte-to-byte delay Response time to read command Response time to read command when 71M6515H is post-processing data CONDITION MIN 19.2 TYP binary 8N1 MAX 38.4 UNIT kBaud
Host sending data to 6515H 6515H sending data to host 6515H has data ready Data not ready CE_ONLY = 1 CE_ONLY = 0 and VAH_SELECT = 0 CE_ONLY = 0 and VAH_SELECT = 1
10 0 0.5
20 0.1 2 40 80 350
ms ms ms ms ms ms
ADC CONVERTER, V3P3 REFERENCED PARAMETER Usable Input Range (Vin-V3P3A) Voltage to Current cross talk: Vin = 200mV peak, 65Hz, on VA, VB, or VC -10 +10 V/V CONDITION MIN -250 TYP MAX 250 UNIT mV peak
10 6 *Vcrosstalk cos(Vin - Vcrosstalk ) Vcrosstalk = largest Vin measurement on IA, IB, or
THD (First 10 harmonics) 250mV-pk 20mV-pk Input Impedance Temperature Coefficient of Input Impedance LSB size Digital Full Scale ADC Gain Error vs. %Power Supply Variation IC Vin=65Hz, 64kpts FFT, BlackmanHarris window Vin=65Hz Vin=65Hz
40 1.7 355 +884736
-75 -90 90
dB dB k /C nV/LSB LSB PPM/ % mV
10 6 Nout PK 357 nV / VIN 100 V 3P3 A / 3.3
Input Offset (Vin-V3P3A)
Vin=200mV pk, 65Hz V3P3A=3.0V, 3.6V -10
50
+10
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MARCH 2008 RECOMMENDED EXTERNAL COMPONENTS NAME C1 C2 XTAL CXS CXL C2P5 FOOTNOTES:
1 This spec is guaranteed, has been verified in production samples, but is not measured in production. 2 This spec is guaranteed, has been verified in production samples, but is measured in production only at DC. 3 This spec is measured in production at the limits of the specified operating temperature. 4 This spec defines a nominal relationship rather than a measured parameter. Correct circuit operation is verified with other specs that use this nominal relationship as a reference
FROM V3P3A V3P3D XIN XIN XOUT V2P5
TO AGND DGND XOUT AGND AGND DGND
FUNCTION Bypass capacitor for 3.3V supply Bypass capacitor for 3.3V supply 32.768kHz crystal - electrically similar to ECS .327-12.5-17X or Vishay XT26T, load capacitance 12.5pF Load capacitor for crystal (depends on crystal specs and board parasitics). Bypass capacitor for V2P5
VALUE 0.120% 0.120% 32.768 2710% 2710% 0.120%
UNIT F F kHz pF pF F
PIN CONFIGURATION AND PIN FUNCTION
RESERVED V3P3A
50
XIN GNDA
XOUT
GNDD
VA
IA
61
51
64
63
62
60
59
58
57
56
55
54
53
GNDD RESERVED TMUXOUT /RTM TX SSCLK CKTEST V3P3D SSDATA SFR RESERVED RESERVED RESERVED RESERVED PULSE3 PULSE4 BAUD_RATE
52
49
GNDA
48 47 46 45 44
VREF
VFLT
VX
VB
VC
IC
IB
1 2 3 4 5 6 7 8 9
GNDD RESETZ V2P5 VBAT RX RESERVED D0 IRQZ PULSE_INIT D6 D5 D4 PULSER PULSEW UARTCSZ D7
TERIDIAN
71M6515H-IGT
43 42 41 40 39 38 37 36 35 34
10 11 12 13 14 15 16 20 21 22 23 24 25 26 27 28 29 30 31 18 17 19
SRDY
MUX_SYNC
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
GNDD
RESERVED
RESERVED
RESERVED
RESERVED
Pins marked RESERVED should be left unconnected during normal use.
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RESERVED
D1
D2
D3
32
33
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71M6515H Energy Meter IC
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MARCH 2008 Analog Pin Description Name IA, IB, IC VA, VB, VC VFLT VX VREF XIN, XOUT Pin No. 56 55 54 53 52 51 59 58 57 61 63 Type I I I I I/O I Circuit 6 6 7 6 9 8 Description Line Current Sense Inputs: Voltage inputs to the internal A/D converter. Typically, they are connected to the output of a current transformer. The input is referenced to V3P3A. Unused pins must be tied to V3P3A. Line Voltage Sense Inputs: Voltage inputs to the internal A/D converter. Typically, they are connected to the output of a resistor divider. The input is referenced to V3P3A. Unused pins must be tied to V3P3A. Power Fault Input. This pin must be tied to V3P3A. Auxiliary input (not used). This pin should be tied to VREF. Voltage Reference for the ADC. Crystal Inputs: A 32768Hz crystal should be connected across these pins. Typically, a 15pF capacitor is also connected from each pin to GNDA. See the datasheet of the crystal manufacturer for details.
Pin types: P = Power, O = Output, I = Input, I/O = Input/Output The circuit number denotes the equivalent circuit, as specified under "I/O Equivalent Circuits".
Digital Pin Description Unless otherwise indicated, all inputs and outputs are standard CMOS. Inputs do NOT have internal pull-ups or pull-downs. Name CKTEST D0 D1 D2 D3 D4 D5 D6 D7 PULSE4 PULSE3 PULSE_INIT BAUD_RATE IRQZ MUXSYNC RESETZ Pin No. 6 42 21 22 23 37 38 39 33 15 14 40 16 41 25 47 Type I/O Circuit 4 Description Clock PLL output. Can be enabled and disabled by CKOUT_DSB (see Status Mask). Input/output pins 0 through 7. These pins must be terminated to V3P3D or ground if configured as input pins. D0 through D7 float after reset or power-up and are configured as outputs and driven low 140ms after RESETZ goes high. The fourth pulse generator output The third pulse generator output The pulse output initial power-up voltage (0: 0V, 1: 3.3V), default is 1. This pin must be terminated to V3P3D or ground. The UART baud rate (1: 38.4kbd, 0: 19.2kbd). This pin must be terminated to V3P3D or ground. Interrupt output, low active. A falling edge indicates the end of a measurement frame, as well as alarms. Rises when status word is read. Internal signal. MUXSYNC falls at the beginning of each conversion cycle (multiplexer frame). Chip reset: Input pin with internal pull-up resistor, used to reset the chip into a known state. For normal operation, this pin is set to 1. To reset the chip, this pin is driven to 0 for 5 microseconds. No external reset circuitry is necessary for power-up reset.
I/O
3, 4
O O I I O O I
4 4 3 3 4 4 1
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71M6515H Energy Meter IC
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MARCH 2008 Pin No. 34 24 9 5 8 44 4 3 36 35
Name UARTCSZ SRDY SFR SSCLK SSDATA RX TX TMUXOUT PULSER PULSEW
Type I I O O O I O O O O
Circuit 3 3 4 4 4 3 4 4 4 4
Description Enables the UART when 0. The UART is disabled when this pin is set to 1. A positive pulse on this pin will reset the UART. This pin must be terminated to ground. High-Speed Synchronous Interface (SSI). The SRDY input should be tied to ground. SSI frame pulse output, one SSCLK wide. SSI clock output (5MHz or 10MHz selectable). SSI data output, changes on the rising edge of SSCLK. UART serial Interface receiver input. The voltage at this pin must not exceed 3.6V. This pin must be terminated to V3P3D or ground. UART serial Interface transmitter output. Digital output test multiplexer. Controlled by TMUX[2:0]. Selectable pulse output (default: VARh pulse). Selectable pulse output (default: Wh pulse).
Power/Ground Pin Description Name GNDA GNDD V3P3A V3P3D VBAT V2P5 Pin No. 49,60 1,27, 48,62 50 7 45 46 Type P P P P P O Description Analog ground: This pin should be connected directly to the ground plane. Digital ground: These pins must be connected directly to the ground plane. Analog power: A 3.3V analog power supply should be connected to this pin. Digital power supply: A 3.3V digital power supply should be connected to this pin. Battery backup power supply. A battery or super-capacitor is to be connected between VBAT and GNDD. If no battery is used, connect VBAT to V3P3D. Output of the 2.5V regulator. A 0.1F capacitor should be connected from this pin to GND.
Pin types: P = Power, O = Output, I = Input, I/O = Input/Output The circuit number denotes the equivalent circuit, as specified under "I/O Equivalent Circuits".
Reserved Pins Pins labeled RESERVED are not to be connected. Name Pin No. 2,10,11,12, 13,17,18,19, 20,26,28,29, 30,31,32,43, 64 Description
RESERVED
DO NOT CONNECT THESE PINS!
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MARCH 2008 I/O Equivalent Circuits
V3P3D V3P3D 110K Digital Input Pin GNDD GNDA Digital Input Equivalent Circuit Type 1: Standard Digital Input or pin configured as DIO Input with Internal Pull-Up V3P3D V3P3A Digital Input Pin GNDD Analog Input Equivalent Circuit Type 6: ADC Input CMOS Input Analog Input Pin To MUX from internal reference V3P3A V3P3D
V2P5 Pin GNDD
V2P5 Equivalent Circuit Type 10: V2P5
CMOS Input 110K GNDD
Comparator Input Pin GNDA
To Comparator
VBAT Pin GNDD
Power Down Circuits
Digital Input Type 2: Pin configured as DIO Input with Internal Pull-Down V3P3D
Comparator Input Equivalent Circuit Type 7: Comparator Input
VBAT Equivalent Circuit Type 12: VBAT Power
V3P3D
Digital Input Pin GNDD
CMOS Input
Oscillator Pin GNDD
To Oscillator
Digital Input Type 3: Standard Digital Input or pin configured as DIO Input V3P3D V3P3D
Oscillator Equivalent Circuit Type 8: Oscillator I/O
V3P3A CMOS Output GNDD GNDD Digital Output Equivalent Circuit Type 4: Standard Digital Output or pin configured as DIO Output Digital Output Pin
from internal reference GNDA
VREF Pin
VREF Equivalent Circuit Type 9: VREF
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71M6515H Energy Meter IC
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MARCH 2008 TYPICAL PERFORMANCE CHARACTERISTICS
0.2 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 0.1
0 Deg 60 Deg -60 Deg 180 Deg
1 0.3 3 10 25 30 100 200
%Error
1
10
A
100
1000
Figure 3: Wh Accuracy, 0.3A - 200A/240V
0.2 0.15 0.1
% Error
90 Deg 150 Deg
3 1 0.3 100 200 10 25 30
0.05 0 -0.05 -0.1 -0.15 -0.2 0.1 1
270 Deg
10
A
100
1000
Figure 4: VARh Accuracy for 0.3A to 200A/240V Performance.
2 1 0 -1
Error [%]
-2 -3 -4 -5 -6 -7 -8 1 3 5 7 9 11 13
Harmonic 50Hz Harmonic Data 60Hz Harmonic Data
15
17
19
21
23
25
Measured at current distortion amplitude of 40% and voltage distortion amplitude of 10%.
Figure 5: Meter Accuracy over Harmonics at 240V, 30A
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y
15 Accuracy [PPM/C] 10 5 0 -5 -10 -15 -60 -40 -20 0 20 40 60 80 100 Temperature [C]
p
(
)
Limit Limit typical chip
MARCH 2008
Figure 6: Typical Meter Accuracy over Temperature Relative to 25C (w/ Temperature Compensation)
Performance for Apparent Energy (VAh)
0.2 Error [%] 0.1 0 -0.1 -0.2 0.1 1 10 Current [A] 100 1000
Figure 7: Typical VAh Accuracy for VAh Using Vector Method
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MARCH 2008 FUNCTIONAL DESCRIPTION THEORY OF OPERATION The 71M6515H integrates the primary functional blocks required to implement a solid-state electricity meter front end. Included on-chip are an analog front end (AFE), a digital computation engine (CE), a voltage reference, a real time clock, and I/O pins. Various current sensor technologies are supported including Current Transformers (CT), Resistive Shunts, and Rogowski (di/dt) Coils. In a typical application, the 71M6515H sequentially digitizes the voltage inputs on pins IA, VA, IB, VB, IC, VC and performs calculations to measure active energy (Wh), reactive energy (VARh), and apparent energy (VAh). In addition to these measurement functions, the real time clock function allows the device to record time of use (TOU) metering information for multi-rate applications. The 71M6515H contains a temperature-trimmed ultra-precise voltage reference, and the on-chip digital temperature compensation mechanism includes a temperature sensor and associated controls for correction of unwanted temperature effects on measurement. RTC accuracy can be greatly improved by supplying correction coefficients derived from crystal characterization. The combination of both features enables designers to produce electricity meters with exceptional accuracy over the industrial temperature range. Meter Equations The 71M6515H implements the equations in Table 1. Register EQU specifies the equation to be used. In one sample time, each of the six inputs is converted and the selected equation updated. In a typical application, IA, IB, IC are connected to current transformers that sense the current on each phase of the line voltage. VA, VB, and VC are typically connected to voltage sensors (resistor dividers) with respect to NEUTRAL. NEUTRAL is to be connected to V3P3A, the analog supply voltage. NEUTRAL is the zero reference for all analog measurements.
EQU
Watt & VAR Formula
Application
Channels used from MUX sequence Mux State: 0 1 VA VA VA VA VA VA 2 IB IB IB IB IB 3 VB VB VB 4 IC IC IC 5 VC VC
0 1* 2 3* 4* 5
VA IA VA(IA-IB)/2 VA IA + VB IB VA (IA - IB)/2 + VC IC VA(IA-IB)/2 + VB(IC-IB)/2) VA IA + VB IB + VC IC
1 element, 2W 1o 1 element, 3W 1o 2 element, 3W 3 oDelta 2 element, 4W 3o Delta 2 element, 4W 3o Wye 3 element, 4W 3o Wye
IA IA IA IA IA IA
Note: Equations 1*, 3*, 4* available only when IMAGE = 00 (CT mode). Table 1: Meter Equations Table 2 shows how the elements of the meter are mapped for the six possible equations.
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71M6515H Energy Meter IC
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MARCH 2008 Element Output Mapping W0SUM/ VAR0SUM VA*IA VA*(IA-IB)/2 VA*IA VA*(IA-IB)/2 VA*(IA-IB)/2 VA*IA W1SUM/ VAR1SUM VA*IB VB*IB VB*(IC-IB)/2 VB*IB VC*IC W2SUM/ VAR2SUM VC*IC I0SQ SUM IA IA-IB IA IA-IB IA-IB IA I1SQ SUM IB IB IB IC-IB IB I2SQ SUM IC IC IC
EQU 0 1 2 3 4 5
Watt & VAR Formula (WSUM/VARSUM) VA IA (1 element, 2W 1) VA*(IA-IB)/2 (1 element, 3W 1) VA*IA + VB*IB (2 element, 3W 3 Delta) VA*(IA-IB)/2 + VC*IC (2 element, 4W 3 Delta) VA*(IA-IB)/2 + VB*(IC-IB)/2 (2 element, 4W 3 Wye) VA*IA + VB*IB + VC*IC (3 element, 4W 3 Wye)
Table 2: Meter Element Output Mapping
ANALOG FRONT END A/D Converter (ADC) A single delta-sigma A/D converter (ADC) digitizes the inputs to the device. The resolution of the ADC is 21 bits. The ADC operates at 5MHz oversampling rate and places the digital results in CE memory. Each analog input is sampled at 2520Hz. Once each accumulation interval, it refreshes the temperature value that is placed in the TEMP_RAW register. The analog reference for all inputs is V3P3A, i.e. the ADC processes voltages between the input pins and V3P3A. Voltage Reference The device includes an on-chip precision bandgap voltage reference that incorporates auto-zero techniques as well as production trims to minimize errors caused by component mismatch and drift. The result is a voltage output with a predictable temperature coefficient. The CE compensates for temperature characteristics of the voltage reference by modifying the gain applied to the V and I channels based on the coefficients PPMC and PPMC2. See the section "TEMPERATURE COMPENSATION" for details. DIGITAL COMPUTATION The six ADC outputs are processed and accumulated digitally. The default product summation is based on 42*60 (if the SUM_CYCLES register is set to 60) samples per accumulation interval. At the end of each accumulation interval, a ready interrupt (IRQZ) is signaled (if enabled with the READY bit in STMASK), indicating that fresh data is available to the host. For instance, if SUM_CYCLES =30, the IRQZ rate will be 2Hz (500ms). A dedicated 32-bit Computation Engine (CE) performs the precision computations necessary to accurately measure energy. Internal CE calculations include frequency-insensitive offset cancellation on all six channels and a frequency insensitive 90 phase shifter for VAR calculations. The CE also includes LPF smoothing filters after each product and squaring circuit to attenuate ripple and eliminate beat frequencies between the power line fundamental and the accumulation time. The CE directly calculates Watts, VARs, V2, and I2 and accumulates them for one interval. At the end of each CE computation cycle, the accumulated data are post-processed to calculate RMS amplitudes, phase angles, and VAh. When post-processing is complete, the IRQZ signal is activated. The minimum combined cycle time for CE and post-processor is 400ms, which makes the maximum frequency for the IRQZ signal 2.5Hz.
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71M6515H Energy Meter IC
DATA SHEET
MARCH 2008 If the 71M6515H is interfacing to an external DSP (typically, but not necessarily through the SSI interface), the host may turn off post-processing by setting the CE_ONLY bit in the CONFIG word. This will permit setting SUM_CYCLES below its recommended lower limit of 24. SUM_CYCLES may then be reduced to 1, creating an accumulation interval of only 42 samples. The outputs available in CE only mode are limited to temperature, frequency, voltage phases, input signal zero crossings, plus WSUM and VARSUM for each phase and VSQSUM, ISQSUM, and ISQFRACT for each phase. Pulse Generators The chip contains four pulse generators connected to the pins PULSEW, PULSER, PULSE3, and PULSE4 that create low jitter pulses from 32-bit data. The peak time jitter for PULSEW and PULSER is the 397s MUX frame period, and is independent of the rate of the generator or the length of time the generator is monitored. Thus, if the pulse generator is monitored for 1 second, the peak jitter is 400PPM. After 10 seconds, the peak jitter is 40PPM. PULSE3 and PULSE4 are updated at a slower rate and have four times higher jitter, i.e. 160PPM after 10 seconds. The average jitter is always zero. If it is attempted to drive either pulse generator faster than its maximum rate, it will simply output at its maximum rate without exhibiting any roll-over characteristics. Pulse generator inputs may be from three sources: * * * Internal (directly from the CE), PULSEW and PULSER only External (controlled by the host writing to registers APULSEW, APULSER, APULSE3, APULSE4) Post-processed values
The source is selected individually for each pulse output with the PULSEW_SRC, PULSER_SRC, PULSE3_SRC, and PULSE4_SRC registers. Figure 8 shows internal pulse generation for the PULSEW output selected by writing the value 35 into the PULSEW_SRC register.
35: WSUM CE
0: WSUM POST PROCESSOR 1: WASUM 2: WBSUM 35 PULSEW_SRC 3: WCSUM 4: VARSUM
PULSEW OUTPUT
34: VAR2SUM_E
36: APULSEW
HOST
Figure 8: Internal Pulse Generation Selected in the PULSEW_SRC Register
Internal data is pulsed out during the accumulation interval immediately following its accumulation interval. Post-processed values are pulsed out one accumulation interval after that.
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
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71M6515H Energy Meter IC
DATA SHEET
MARCH 2008 The pulse generator output rate depends on its input value, WRATE, PULSE_SLOW, and PULSE_FAST. Additionally, its maximum pulse width (negative going pulse) is controlled by PULSEWIDTH. High frequency pulses will have 50% duty cycle until their rate slows enough that their pulse width is limited by PULSEWIDTH. In internal and post-processed modes, the pulse rate, expressed as Kh (Wh per pulse) is given by the formula:
Kh =
VMAX IMAX 1.5757 Wh / Pulse In _ 8 SUM _ CYCLES WRATE X
where VMAX is the meter voltage corresponding to an input voltage of 176mV (rms) at the VA, VB, and VC input pins , IMAX is the meter current corresponding to an input voltage of 176mV (rms) at the IA, IB, and IC input pins, In_8 is the additional ADC gain (1 or 8), as controlled by the IA_X, IB_X and IC_X bits in the CONFIG register. X is the pulse speed factor determined from Table 3. PULSE_SLOW 0 0 1 1 (default) PULSE_FAST 0 1 0 1 (default) X 1.5*22=6 1.5*26=96 1.5*2-4=0.09375 1.5
Table 3: Pulse Speed Factor X In external pulse mode, the pulse rate is given by the formula: Rate(Hz) = WRATE * X * input * 35.82*10-12, where input is the value in registers APULSER, APULSEW. APULSE3 or APULSE4, X is the pulse speed factor determined from Table 3. External pulse generation can be seen as providing the raw voltage and current readings equivalent to Vin*Iin / LSB directly to the pulse generator. The maximum pulse rate is 7.56kHz for PULSEW and PULSER, and 150Hz for PULSE3 and PULSE4. In external pulse mode, the pulse generators load their data at the beginning of each CE accumulation interval, preserving any partially implemented pulses from the previous interval. The source of data is controlled by the entries in the PULSE_SRCS register. PULSER_SRCS contains 8-bit entries for each pulse source, PULSEW, PULSER, PULSE3, and PULSE4. See the register description for details. The procedure for accurate external pulse generation controlled by the host is: 1) 2) 3) Respond to a READY interrupt by reading the accumulated values. Process the accumulated values. Write the processed value(s) to APULSER, APULSEW, APULSE3, or APULSE4. The host must write to APULSER, APULSEW, APULSE3, and APULSE4 before the next READY interrupt for the pulse generation to be beginning in the following accumulation interval.
Figure 9 illustrates pulse generator timing. Regardless of the source, the pulse generators should receive new data during each accumulation interval. If this does not occur and if the corresponding bit in the STMASK register is set, an APULSE_ERR interrupt will be issued. The PULSEW, PULSER, PULSE3 and PULSE4 pins are suitable for driving LEDs through a current limiting resistor. The LED should be connected so it is on when the pulse pin is low. The pin PULSE_INIT determines the logic level applied to the pulse pins on power-up, i.e. with PULSE_INIT low, the pulse pins will be initialized to low (default = 1).
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
V1.4
71M6515H Energy Meter IC
DATA SHEET
MARCH 2008 The pulse width PW is controlled with the PULSEWIDTH register for the PULSER and PULSEW output pins per the following formula:
PW =
2 PULSEWIDTH + 1 2520.6
Internal Data (Directly by CE)
Accumulation Interval CE Operations XFER Post Processing Post 0 READY Pulse Generator Pulse 0 Accumulation 1 XFER Post 1 READY Pulse 1 Accumulation 2 XFER Post 2 READY Pulse 2 Accumulation 3
The PULSE3 and PULSE4 output pins will always generate pulses with 50% duty cycle.
Post-Processed Data
Accumulation Interval CE Operations XFER Post Processing Post 0 READY Pulse Generator APULSE write Pulse -1 Accumulation 1 XFER Post 1 READY APULSE write Pulse 0 Accumulation 2 XFER Post 2 READY APULSE write Pulse 1 Accumulation 3
External (Host data is transferred to the pulse generator in the first accumulation interval after the next READY)
Accumulation Interval CE Operations XFER Post Processing Host Processing Pulse Generator Post 0 READY Host 0 APULSE write Pulse -2 Accumulation 1 XFER Post 1 READY Host 1 APULSE write Pulse -1 Accumulation 2 XFER Post 2 READY Host 2 APULSE write Pulse 0 Accumulation 3
Figure 9: Pulse Generator Timing
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
V1.4
71M6515H Energy Meter IC
DATA SHEET
MARCH 2008 Internal Resources Oscillator The oscillator drives a standard 32.768kHz watch crystal. Crystals of this type are accurate and do not require a high current oscillator circuit. The 71M6515H oscillator has been designed specifically to handle watch crystals and is compatible with their high impedance and limited power handling capability. The oscillator power dissipation is very low to maximize the lifetime of any battery backup device attached to VBAT. Using PLL techniques, all internal clocks, such as the 4.915MHz clock for the ADC and the post-processor, are derived from the watch crystal frequency. Real-Time Clock (RTC) The RTC is driven directly by the crystal oscillator. In the absence of V3P3, it is powered by the battery-backed up supply. The RTC consists of a counter chain and output registers. The counter chain consists of registers for seconds, minutes, hours, day of week, day of month, month, and year. The nominal quadratic temperature coefficient of the crystal is automatically compensated in the RTC. The RTC is capable of processing leap years. I/O Peripherals The 71M6515H includes several I/O peripheral functions that improve the functionality of the device and reduce the component count for most meter applications. The I/O peripherals include a UART and digital I/O. Digital I/O The device includes eight pins of general purpose digital I/O (D0...D7). Each pin can be configured independently as an input or output with the D_DIR bits. Inputs are standard CMOS with no pull-ups or pull-downs. Outputs are standard CMOS. The DIO pins are controlled by the D_CONFIG register. Immediately after reset or power-up, D0 through D7 are in tri-state mode (floating). 140 ms after reset, D0 through D7 are configured as outputs and driven low. UART Host Interface The UART is a dedicated 2-wire serial interface, which can communicate with the host processor. The operation of each pin is as follows: RX: Is the pin accepting the serial input data. It inputs data to internal registers. The bytes are input LSB first. The voltage applied to this pin must be restricted to 0 to 3.6V. TX: Is the pin used for serial output data. It outputs the contents of a block of internal registers. The bytes are output LSB first. BAUD_RATE: The baud rate can be selected with the BAUD_RATE pin (38.4bps when high, 19.2bps when low). UARTCSZ: This pin enables the UART when low. The UART can be reset by taking UARTCSZ briefly to the high state and then low again. The 71M6515H has several on-chip registers, which can be read and written. All transfers start with a stream of 8-bit bytes (LSB first) from the host on the RX input, followed by a (possibly null) stream of 8-bit bytes (LSB first) to the host on the TX output (see Figure 10 and Figure 11). The UART is configured as 8N1 (8 bits, no parity, 1 stop bit). If the READY bit in STMASK is enabled, the IRQZ pin can be used to signal data availability to the host. If data read cycles exceeding 1 second are used, care should be taken to prevent data overflow. UART Write Register Operation The registers are written by sending a byte, consisting of a starting register address in the seven MSBs and `0' in the LSB indicating this is a write operation. It is followed by a one byte length of bytes to write. If more bytes arrive than fit in the addressed register, subsequent registers will be written. The bytes are processed in "big-endian" order (i.e. most significant byte first). See Figure 10 (read bits and bytes from left to right).
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
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71M6515H Energy Meter IC
DATA SHEET
MARCH 2008
L WS B M S B L S B M S B L S B M S B L S B M S B
RX register address time length most significant data byte least significant data byte
TX
Figure 10: UART Write Operation
UART Read Register Operation The registers are read by sending a byte, consisting of a start register address in the seven MSBs and `1' in the LSB indicating this is a read operation. It is followed by a one byte length of bytes to read. If more bytes are asked for than the size of the addressed register, subsequent registers will be read. The bytes are in "big-endian" order (i.e. most significant byte first). See Figure 11.
L RS B
M S B
L S B
M S B
RX register address time
L S B M S B L S B M S B
length
TX
most significant data byte
least significant data byte
Figure 11: UART Read Operation Note: In both register read and write operations, the register address can be 0 through 127 (0x7F). The register address byte is obtained by left-shifting the register address by one bit and setting bit 0 to 1 for read or setting bit 0 to 0 for write. Synchronous Serial Interface (SSI) A high speed, handshake, serial interface is available to send a contiguous block of CE data to an external data logger or DSP. The block of data, configurable as to location and size, is sent at the beginning of each ADC multiplex cycle. The SSI interface is enabled by the SSI_EN bit and consists of the outputs SSCLK, SSDATA, and SFR and of the SRDY input pin. The interface is compatible with 16-bit and 32-bit processors. The operation of each pin is as follows: SSCLK: This pin provides the serial clock. The clock can be 5MHz or 10MHz, as specified by the SSI_10M bit. The SSI_CKGATE bit controls whether SSCLK runs continuously or is gated off when no SSI activity is occurring. If SSCLK is gated, it will begin three cycles before SFR rises and will persist three cycles after the last data bit is output. SSDATA: This pin provides the serial output data. SSDATA changes on the rising edge of SSCLK and outputs the contents of a block of CE words starting with address SSI_STRT and ending with SSI_END. The words are output MSB first. SSDATA is stable with the falling edge of SSCLK. SFR: This pin provides the framing pulse. Although CE words are always 32 bits, the SSI interface will frame the entire data block as a single field, as multiple 16 bit fields, or as multiple 32 bit fields. The SFR pulse is one clock cycle wide, changes state on the rising edge of SSCLK and precedes the first bit of each field. The field size is set with SSI_FSIZE: 0-entire data block, 1-8 bit fields, 2-16 bit fields, 3-32 bit fields. The polarity of the SFR pulse can be inverted with SSI_FPOL. The first SFR pulse in a frame will rise on the third SSCLK clock period after MUX_SYNC (fourth SSCLK period, if SSCLK is 10MHz). MUX_SYNC can be used to synchronize the fields arriving at the data logger or DSP. SRDY: The SRDY input should always be tied to GND.
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71M6515H Energy Meter IC
DATA SHEET
MARCH 2008 The SSI timing is shown in Figure 12.
If SSI_CKGATE =1 SFR (Output) SCLK (Output) SSDATA (Output) MUX_STATE 31 30 16 15
If 16bit fields
If 32bit fields
If SSI_CKGATE =1
1
0
31
30
16
15
1
0
31
1 SSI_END
0
SSI_BEG
SSI_BEG+1
Figure 12: SSI Timing (SSI_FPOL = SSI_RDYPOL = 0) Fault and Reset Behavior Reset Mode When RESETZ is pulled low or when VFLT < V3P3/2, all activity (i.e. sampling of analog signals, CE, generation of digital outputs) in the chip stops while the analog circuits are active. The exceptions are the oscillator and RTC module, which continue to run. Additionally, all I/O Register bits are cleared. As long as VFLT > V3P3/2, the internal 2.5V regulator will continue to provide power to the digital section. Once initiated, the reset mode will persist until the reset timer times out. This will occur in 4100 cycles of the real time clock after RESETZ goes high, at which time the 71M6515H will begin executing its preboot and boot sequences. Power Fault Circuit The power fault comparator compares the voltage at the VFLT pin to V3P3/2. The comparator output internally enables the battery backup protection for oscillator, RTC and RAM during the power fail mode. Temperature Compensation Voltage Reference The internal voltage reference of the 71M6515H is calibrated at 25C during device manufacture. The 71M6515H is given additional temperature-related calibrations which further compensate its ADC gain and allow it to achieve 10PPM/C over 60C temperature range. Temperature Sensor The device includes an on-chip temperature sensor for determining the temperature of the bandgap reference. The primary use of the temperature data is to determine the magnitude of compensation required to offset thermal drift in the system. The temperature sensor is read once per accumulation interval. Temperature measurement can be implemented with the following steps: 1) 2) 3) At a known temperature TN, read the TEMP_RAW register and write the value into TEMP_NOM register. Read the DELTA_T register at the known temperature. The obtained value should be <0.1C. The temperature T (in C) at any environment can be obtained by reading the DELTA_T register and applying the following formula:
T = TN +
DELTA _ T 10
Temperature Compensation for Energy Measurements TEMP_NOM is one of the calibration parameters that must be loaded by the host in order to enable temperature measurement and thereby temperature compensation.
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
V1.4
71M6515H Energy Meter IC
DATA SHEET
MARCH 2008 PPMC and PPMC2, the linear and quadratic compensation coefficients, compensate for temperature drift in the 71M6515H reference that affects the meter performance. PPMC and PPMC2 describe how the 71M6515H calculations are to respond to temperature. This means they should be the negative of the meter behavior before compensation. PPMC and PPMC2 are scaled from PPM/C and PPM/C2 values. See the register description for details. Temperature compensation can be selected to operate in one of two modes shown in the table below:
Temperature Compensation Mode Internal (CE) External (host)
DEFAULT_PPM Bit in CONFIG Register 1 0
PPMC, PPMC2 Calculation By post-processor, based on stored VREF characteristics By host
When the part is first powered up, TEMP_NOM, PPMC, and PPMC2 are zero. When the host writes its calibration value into TEMP_NOM (after setting the DEFAULT_PPM bit on the CONFIG register to 1), PPMC and PPMC2 will automatically be initialized to the values that best compensate for the temperature drift of the internal reference. These parameters will be individually customized for 71M6515H parts. If, for some reason, the host writes to TEMP_NOM again, PPMC and PPMC2 will not be changed since they will no longer be zero. If TEMP_NOM is not loaded by the host, PPMC and PPMC2 are ignored, and their values are permanently held at zero. If TEMP_NOM is zero, no temperature compensation occurs, even if PPMC and PPMC2 are loaded. If the host wishes to provide its own compensation, it should read PPMC and PPMC2 and modify them by merging the additional compensation into to them. In that case, the DEFAULT_PPM bit in the CONFIG register must be zero. Temperature Compensation for the Crystal and RTC The crystal oscillator contributes negligible error to energy calculations. However, sometimes specifications for the real time clock (RTC) require better accuracy than that provided by the untrimmed watch crystal. The 71M6515H therefore allows calibration of the RTC clock. Calibration requires that frequency tolerance and frequency stability either be obtained from the manufacturer or be independently measured (the RTC clock is available on the TMUX pin). Calibration does not change the frequency of the RTC clock, but rather increments or decrements the clock by one second when sufficient error has accumulated. Positive correction makes the clock run faster. The formula for the RTC correction factor is as follows: CORRECTION [PPM] = Where
Y _ CALC 0 Y _ CALC1 T Y _ CALC 2 T 2 + + 10 100 1000
Y_CALC0 = 10 * crystal frequency deviation from ideal (measured) Y_CALC1 = 100 * crystal skew (nominally zero) Y_CALC2 = 1000 * crystal frequency stability (specified) T = T - Calibration Temperature in C Calibration
Calibration Factors for CT and Resistive Shunt Once installed in a meter, the TERIDIAN 71M6515H IC has to be calibrated for the tolerances of current sensors, voltage dividers and signal conditioning components. The room temperature reading of its temperature sensor must also be entered. These calibration factors must be stored by the host and, upon power up, loaded into the TERIDIAN 71M6515H. Typical calibration constants are listed in Table 4.
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
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71M6515H Energy Meter IC
DATA SHEET
MARCH 2008 Name CAL_IA CAL_VA CAL_IB CAL_VB CAL_IC CAL_VC TEMP_NOM PHADJ_A PHADJ_B PHADJ_C Description
Gain factors for current and voltage of each phase.
The value of TEMP_RAW at nominal temperature. Phase compensation for each current. If phase compensation is 0 or if current sensors have predictable phase, PHADJ may not need to be measured on every meter. Table 4: Typical Calibration Parameters (CT)
Gain adjustment (CAL_Xn parameters) is used to compensate for tolerances of components used for signal conditioning, especially the resistive components. A 1% increase in CAL_Xn will cause a 1% increase in the channel gain. The phase compensation circuit in the TERIDIAN 71M6515H is optimized for operation with current transformers (CT's). These devices have a low frequency pole and therefore have a slight amount of phase lead at 50 or 60Hz--more at 50Hz than at 60Hz. The phase lead diminishes at higher harmonics. When PHADJ_n is calibrated as shown below at either 50Hz or 60Hz, the CT will be correctly compensated from below 25Hz to beyond 1100Hz. This phase compensator is markedly superior to the more common technique of programming a time delay to compensate for CT phase. The time delay technique results in phase compensation that is correct at only one frequency, and actually amplifies the phase error at harmonics of the frequency. Calibration Factors for Rogowski Coil Sensors If IMAGE is set to 01, i.e. the 71M6515H can be operated with Rogowski Coil sensors. In this case, one more calibration factor per phase is needed. The PHADJ parameters have non-zero defaults and do not obey the same formula used for CT calibration. The feedthrough parameter has to be determined by a separate crosstalk measurement. Table 5 shows the parameters involved in the calibration procedure for the Rogowski sensor.
Name CAL_IA CAL_VA CAL_IB CAL_VB CAL_IC CAL_VC TEMP_NOM PHADJ_A PHADJ_B PHADJ_C VFEED_A VFEED_B VFEED_C
Description
Gain constants for current and voltage of each phase.
The value of TEMP_RAW at nominal temperature. Phase compensation for each current. If phase compensation is 0 or if current sensors have predictable phase, PHADJ may not need to be measured on every meter. Feedthrough compensation for each current. Table 5: Typical Calibration Parameters (Rogowski)
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
V1.4
71M6515H Energy Meter IC
DATA SHEET
MARCH 2008 General Notes on Calibration The calibration procedures described below should be followed after interfacing the voltage and current sensors to the 71M6515H chip. When properly interfaced, the V3P3 power supply is connected to the meter neutral and is the DC reference for each input. Each voltage and current waveform, as seen by the 6515H, is scaled to be less than 250mV (peak). Each meter phase must be calibrated individually. The procedures below show how to calibrate a meter phase with either three or five measurements. Note that there is no need to calibrate for VARh if the Wh measurement is calibrated correctly. Note that positive load angles correspond to lagging current (see Figure 13). For a typical calibration, a meter calibration system is used to apply a calibrated load, e.g. 240V at 30A, while interfacing the voltage and current sensors to the 71M6515H. This load should result in an observable pulse rate at the PULSEW output depending on the selected energy per pulse. For example, 7.2kW will result in an energy rate corresponding to 7200Wh/3600s = 2Wh/s, i.e., when 7.2kW are applied per phase (resulting in a total power of 21.6kW, equivalent to 6Wh/s) and a Kh of 3.2 (Wh/pulse) has been configured, a pulse rate of 6Wh/3.2Whs
Voltage
Positive direction
Current lags voltage (inductive)
+60 -60
Current
Current leads voltage (capacitive)
Voltage Generating Energy Using Energy
= 1.875Hz will be established. Figure 13: Definition of Load Angles It is entirely possible to calibrate piece-wise, i.e. in segments, to compensate for non-linear sensors. For example, one set of calibration factors can be applied by the host when the current is below 0.5A, while another set is applied when the current is at or above 0.5A. Calibration Procedure for CT and Resistive Shunt A typical meter has phase and gain errors as shown by S, AXI, and AXV in Figure 14. Following the typical meter convention of current phase being in the lag direction, the small amount of phase lead in a typical current sensor is represented as -S. The errors shown in Figure 14 represent the sum of all gain and phase errors. They include errors in voltage attenuators, current sensors, signal conditioning circuits, and in ADC gains. In other words, no errors are made in the `input' or `meter' boxes.
INPUT I L ERRORS -S S is phase lead A XI METER IRMS
IDEAL = I ,
L is phase lag
ACTUAL = I AXI
V AXV
W
IDEAL = IV cos( L )
ACTUAL = IV AXI AXV cos( L - S ) IDEAL = V , ACTUAL = V AXV
V RMS
ERROR
ACTUAL - IDEAL ACTUAL -1 = IDEAL IDEAL
Figure 14: Watt Meter with Gain and Phase Errors. During the calibration phase, we measure errors and then introduce correction factors to nullify their effect. With three unknowns to determine, we must make at least three measurements. If we make more measurements, we can average the results.
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
V1.4
71M6515H Energy Meter IC
DATA SHEET
MARCH 2008 Calibration with Three Measurements The simplest calibration method is to make three measurements. Typically, a voltage measurement and two Watt-hour (Wh) measurements are made. If the voltage measurement has the error EV and the two Wh measurements have errors E0 and E60, where E0 is measured with L = 0 and E60 is measured with L = 60. These values should be simple ratios--not percentage values. They should be zero when the meter is accurate and negative when the meter runs slow. The fundamental frequency is f0. T is equal to 1/fS, where fS is the sample frequency (2520.62Hz). Set all calibration factors to nominal: CAL_IA = 16384, CAL_VA = 16384, PHADJ_A = 0. From the voltage measurement, we determine that 1.
AXV = EV + 1
IV AXV AXI cos(0 - S ) - 1 = AXV AXI cos( S ) - 1 IV cos(0)
E0 + 1 cos( S )
We use the other two measurements to determine S and AXI. 2.
E0 =
2a.
AXV AXI =
3.
E 60 =
IV AXV AXI cos(60 - S ) cos(60 - S ) - 1 = AXV AXI -1 IV cos(60) cos(60)
3a.
E 60 =
AXV AXI [cos(60) cos( S ) + sin(60) sin( S )] -1 cos(60)
= AXV AXI cos( S ) + AXV AXI tan(60) sin( S ) - 1
Combining 2a and 3a: 4. 5.
E 60 = E 0 + ( E 0 + 1) tan(60) tan( S )
tan( S ) = E 60 - E 0 ( E 0 + 1) tan(60)
E 60 - E 0 ( E 0 + 1) tan(60)
6.
S = tan -1
and from 2a: 7.
AXI =
E0 + 1 AXV cos( S )
Now that we know the AXV, AXI, and S errors, we calculate the new calibration voltage gain coefficient from the previous ones:
CAL _ V NEW =
CAL _ V AXV
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71M6515H Energy Meter IC
DATA SHEET
MARCH 2008 We calculate PHADJ from S, the desired phase lag:
20
tan( S ) 1 + (1 - 2 -9 ) 2 - 2(1 - 2 -9 ) cos(2f 0T ) PHADJ = 2 -9 -9 (1 - 2 ) sin(2f 0T ) - tan( S ) 1 - (1 - 2 ) cos(2f 0T )
[
[
]
]
Finally, we calculate the new calibration current gain coefficient, including compensation for a slight gain increase in the phase calibration circuit.
CAL _ I NEW =
CAL _ I AXI
1 1+ 2
- 20
PHADJ (2 + 2 PHADJ - 2(1 - 2 -9 ) cos(2f 0T )) 1 - 2(1 - 2 -9 ) cos(2f 0T ) + (1 - 2 -9 ) 2
- 20
Calibration with Five Measurements The five measurement method provides more orthogonality between the gain and phase error derivations. This method involves measuring EV, E0, E180, E60, and E300. Again, set all calibration factors to nominal, i.e. CAL_IA = 16384, CAL_VA = 16384, PHADJ_A = 0.. First, calculate AXV from EV: 1.
AXV = EV + 1
IV AXV AXI cos(0 - S ) - 1 = AXV AXI cos( S ) - 1 IV cos(0)
Calculate AXI from E0 and E180: 2.
E0 =
3. 4. 5.
E180 =
IV AXV AXI cos(180 - S ) - 1 = AXV AXI cos( S ) - 1 IV cos(180)
E 0 + E180 = 2 AXV AXI cos( S ) - 2
AXV AXI =
AXI =
E 0 + E180 + 2 2 cos( S )
6.
( E 0 + E180 ) 2 + 1 AXV cos( S )
Use above results along with E60 and E300 to calculate S. 7.
E 60 =
IV AXV AXI cos(60 - S ) -1 IV cos(60)
= AXV AXI cos( S ) + AXV AXI tan(60) sin( S ) - 1
8.
E 300 =
IV AXV AXI cos( -60 - S ) -1 IV cos( -60)
= AXV AXI cos( S ) - AXV AXI tan(60) sin( S ) - 1
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
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71M6515H Energy Meter IC
DATA SHEET
MARCH 2008 Subtract 8 from 7: 9.
E 60 - E300 = 2 AXV AXI tan(60) sin( S )
E 0 + E180 + 2 tan(60) sin( S ) cos( S )
use equation 5: 10.
E 60 - E300 =
11. 12.
E 60 - E300 = ( E 0 + E180 + 2) tan(60) tan( S )
S = tan -1
( E 60 - E300 ) tan(60)( E 0 + E180 + 2)
Now that we know the AXV, AXI, and S errors, we calculate the new calibration voltage gain coefficient from the previous ones:
CAL _ V NEW =
CAL _ V AXV
We calculate PHADJ from S, the desired phase lag:
tan( S ) 1 + (1 - 2 -9 ) 2 - 2(1 - 2 -9 ) cos(2f 0T ) PHADJ = 2 20 -9 -9 (1 - 2 ) sin(2f 0T ) - tan( S ) 1 - (1 - 2 ) cos(2f 0T )
[
[
]
]
Finally, we calculate the new calibration current gain coefficient, including compensation for a slight gain increase in the phase calibration circuit.
CAL _ I NEW =
CAL _ I AXI
1 1+ 2
- 20
PHADJ (2 + 2 PHADJ - 2(1 - 2 -9 ) cos(2f 0T )) 1 - 2(1 - 2 -9 ) cos(2f 0T ) + (1 - 2 -9 ) 2
- 20
Alternative Calibration Procedures It is possible to implement a fast calibration based on only one measurement with a zero-degree load angle. Details can be found in the TERIDIAN Application Note AN_651X_022 (Calibration Procedures). Calibration Procedure for Rogowski Sensor Rogowski coils generate an output signal that is the derivative of the input current. The 6515H Rogowski module implemented in the Rogowski CE image digitally compensates for this effect and has the usual gain and phase calibration adjustments. Additionally, calibration adjustments are provided to eliminate voltage coupling from the sensor input. Current sensors built from Rogowski coils have relatively high output impedances that are susceptible to capacitive coupling from the large voltages present in the meter. The most dominant coupling is usually capacitance between the primary of the coil and the coil's output. This coupling adds a component proportional to the derivative of voltage to the sensor output. This effect is compensated by the voltage coupling calibration coefficients. As with the CT procedure, the calibration procedure for Rogowski sensors uses the meter's display to calibrate the voltage path and the pulse outputs to perform the remaining energy calibrations. The calibration procedure must be performed to each phase separately, making sure that the pulse generator is driven by the accumulated real energy for just that phase. In other words, the pulse generator input should be set to WhA, WhB, or WhC, depending on the phase being calibrated. The IC has to be configured for Rogowski mode (IMAGE=01). In preparation of the calibration, all calibration parameters are set to their default values. VMAX and IMAX are set to reflect the system design parameters. WRATE and PULSE_SLOW, PULSE_FAST are adjusted to obtain the desired Kh. For details on calibrating a meter for Rogowski coil sensors, see the TERIDIAN Application Note AN_6515_036.
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MARCH 2008 Meter Design - Scaling of Measured Values An actual meter will always use sensors that scale the voltages and currents managed by the meter to small voltages that can be processed by the 71M6515H. This scaling is reflected in the system parameters VMAX and IMAX. Scaling is physically implemented with resistor dividers for the voltage signals and current transformers, shunt resistors or Rogowski coils for the current signals. IMAX is the RMS meter current that results in 250mV peak signal (or 177mV RMS) at the ADC input (IA, IB, IC pins). VMAX is the RMS meter voltage that results in 250mV peak signal at the ADC input (VA, VB, VC pins). In_8 is either 1 or 8, depending on In_8x, the ADC gain configuration bit for element n (see IA_8, IB_8, IC_8) in the CONFIG register. Only the host is aware of the system parameters VMAX and IMAX, while the CE and the post-processor know signal amplitudes only as values relative to their maximum peak levels (250mV). This makes the host itself responsible for translating the measured values from the 71M6515H registers into real-world values by applying the parameters VMAX, IMAX and In_8. Equally, the host is responsible for non-volatile storage of accumulated energy values, calibration factors, default settings et cetera. Measured values and values determining the function of the 71M6515H, as controlled by the registers described in the following section, are often stated as fractions or multiples of the system parameters VMAX, IMAX and In_8. Host Interface - REGISTER DESCRIPTION Communication between the host and the 71M6515H is established by writing to and reading from the registers described in this section. The registers are accessible via the UART (see UART Write and Read Operation). The tables below contain the registers that can be accessed by the host to obtain data from the 71M6515H or to control and configure the IC. Bits with a W (write) direction are written by the host. Bits with R (read) direction can only be read by the host. Write operations attempted to read-only registers will result in the CMD_IGNORED bit set in the STATUS register. Unless stated otherwise, all registers are four bytes (32 bits), 2's complement, and have a range of (231-1) to -(231-1). Register Groups Each register belongs to one of the following functional groups: * * * * * * * * * * * Pulse Generation Calibration Control of Basic Functions Temperature Temperature Compensation Output Signals Accumulated Energy and V/I Values Alarms and Thresholds Time (RTC) Test Digital I/O Control (pins D0...D7)
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MARCH 2008 Registers in Alphabetical Order Name APULSEW APULSER APULSE3 APULSE4 CAL_IA CAL_VA CAL_IB CAL_VB CAL_IC CAL_VC CE_DATA CE_DATA_ADDR CE_DATA_INC CE_PROG CE_PROG_ADDR CE_PROG_INC CONFIG CREEP_THRSLD DEG_SCALE D_CONFIG FREQ_DELTA_T GAIN_ADJ IASQFRACT IBSQFRACT ICSQFRACT IASQSUM IBSQSUM ICSQSUM INSQFRACT INSQSUM IPHASE_ABC IRMS_A IRMS_B IRMS_C KVAR MAIN_EDGE_ COUNT OP_TIME Address (hex) 0x30 0x31 0x32 0x33 0x24 0x25 0x26 0x27 0x28 0x29 0x63 0x61 0x65 0x62 0x60 0x64 0x16 0x1D 0x1C 0x1A 0x11 0x4E 0x4A 0x4B 0x4C 0x39 0x3A 0x3B 0x4D 0x3C 0x0F 0x0C 0x0D 0x0E 0x2F 0x35 0x1E R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R R R R R R R R R/W Default 0 0 0 0 214 214 214 214 214 214 N/A N/A N/A N/A N/A N/A 0 6000 22721 15 N/A 16384 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 6444 N/A 0 Group Comment
Pulse Generation Control
Calibration Calibration Calibration Control of Basic Functions Control of Basic Functions Control of Basic Functions Control of Basic Functions Control of Basic Functions Control of Basic Functions Control of Basic Functions Alarms and Thresholds Temperature I/O Control Outputs, Temperature Temperature Compensation Outputs
Outputs Outputs Outputs Outputs Outputs Calibration Outputs Time Uses the postprocessor Uses the postprocessor Do not change
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MARCH 2008 Address (hex) 0x2A 0x2B 0x2C 0x1B 0x42 0x43 0x41 0x34 0x36 0x37 0x38 0x20 0x1F 0x21 0x2E 0x22 0x14 0x15 0x13 0x12 0x3D 0x3E 0x3F 0x06 0x07 0x08 0x03 0x04 0x05 0x44 0x45 0x46 0x17 0x40
Name PHADJ_A PHADJ_B PHADJ_C PPMC1_2 PULSE3_4_ CNTS PULSE_SRCS PULSEW_R_ CNTS PULSE_WIDTH QUANT_W QUANT_VAR QUANT_I RTC_DATE RTC_TIME_DAY RTM SAG SSI STATUS STMASK TEMP_NOM TEMP_RAW VASQSUM VBSQSUM VCSQSUM VAH_A VAH_B VAH_C VARH_A VARH_B VARH_C VFEED_A VFEED_B VFEED_C VI_PTHRESH VI_THRESH
R/W R/W R/W R/W R/W R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R R R R R R R R R R R/W R/W R/W W W
Default CT: 0 CT: 0 CT: 0 0 N/A N/A 50 0 0 0 N/A N/A 0 80, 26000 0 N/A 0 0 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 0 0 0 21000 21000
Group Calibration Temperature Compensation Outputs Pulse Generation Control Outputs Pulse Generation Control Calibration Time Time Test Alarms and Thresholds Test Control of Basic Functions Control of Basic Functions Outputs Outputs Outputs
Comment Defaults are -3973 for Rogowski operation
Outputs
Uses the postprocessor
Outputs
Calibration Alarms and Thresholds Alarms and Thresholds
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MARCH 2008 Address (hex) 0x10 0x09 0x0A 0x0B 0x00 0x01 0x02 0x2D 0x18 0x19 Name VPHASE_ABC VRMS_A VRMS_B VRMS_C WH_A WH_B WH_C WRATE Y_DEG0 Y_DEG1_2 R/W R R R R R R R R/W R/W R/W Default N/A N/A N/A N/A N/A N/A N/A 683 0 0 Group Outputs Outputs Uses the postprocessor Comment
Outputs Pulse Generation Control Temperature Compensation Temperature Compensation Holds Y_CALC0 Holds Y_CALC1 and Y_CALC2
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MARCH 2008 Individual Register Descriptions Registers for Pulse Generation Control APULSEW (0x30), APULSER (0x31), APULSE3 (0x32), APULSE4 (0x33), Figure 15 shows the registers that control the PULSEW, PULSER, PULSE3 and PULSE4 output pins if the corresponding PULSE_SRCS register contains the decimal value 36. This figure uses the PULSER_SRC 8-bit portion of the PULSE_SRCS register as an example: The internal pulse generation (CE) and the post-processor pulse generation are deselected, and the APULSER register acts as the pulse generation source. In this setting (external pulse generation), the host is responsible for updating the data in the APULSER register.
35: WSUM CE
0: WSUM POST PROCESSOR 1: WASUM 2: WBSUM 36 PULSER_SRC 3: WCSUM 4: VARSUM
PULSER OUTPUT
34: VAR2SUM_E 34: VAR2SUM_E
36: APULSER
HOST
Figure 15: Pulse Generation via APULSER Selected in the PULSER_SRC Register PULSE_SRCS (0x43) This register contains the pulse source selectors for the pulses generated by the PULSEW, PULSER, PULSE3 and PULSE4 output pins. Pulse sources can be selected individually for internal (CE), external (post-processor) or external (supplied by the host). The internal selection is valid for the PULSER and PULSEW generators only. The allocation of the bytes in PULSE_SRCS is as follows: 31 PULSEW_SRC Source selector register for the PULSEW generator 24 23 PULSER_SRC Source selector register for the PULSER generator 16 15 PULSE3_SRC Source selector register for the PULSE3 generator 8 7 PULSE4_SRC Source selector register for the PULSE4 generator 0
Table 6 shows the codes used to select pulse sources. PULSE_WIDTH (0x34) This register contains the numerical value controlling the pulse width for the PULSEW and PULSER output pins. The default value is 50, which amounts to 40.07ms. The pulse width PW follows the formula: PW <= (2 * PULSE_WIDTH + 1)/2520.6
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MARCH 2008 At high pulse rates, duty cycle is 50%. At rates less than 1/(2*PWmax), the negative going pulse width is PWmax. The 31 allowed range is 0 to 2 -1. The pulse width for the PULSE3 and PULSE4 outputs is always at a 50% duty cycle. The initial voltage level of the pulse pins is defined with the PULSE_INIT pin. Value in Pulse Source Register (hex) (dec) 0x00 0 0x01 1 0x02 2 0x03 3 0x04 4 0x05 5 0x06 6 0x07 7 0x08 8 0x09 9 0x0A 10 0x0B 11 0x0C 0x0D 0x0E 0x0F 12 13 14 15 Name WSUM WASUM WBSUM WCSUM VARSUM VARASUM VARBSUM VARCSUM VASUM VAASUM VABSUM VACSUM INSQSUM IASQSUM IBSQSUM ICSQSUM Description The signed sum: W0SUM + W1SUM + W2SUM The sum of Wh samples from individual wattmeter elements. LSB = 9.4045*10-13 VMAX IMAX / In_8 Wh The signed sum: VAR0SUM + VAR1SUM + VAR2SUM The sum of VARh samples from individual wattmeter elements. LSB = 9.4045*10-13 VMAX IMAX / In_8 VARh The sum of VAh samples from individual samples. The sum of VAh samples from individual wattmeter elements. LSB = 9.4045*10-13 VMAX IMAX / In_8 VAh The sum of the square of the calculated neutral current. ( I0 + I1 + I 2 )2.
LSB = 9.4045*10-13 IMAX2 / In_82 A2h
The sum of squared current samples from each element. LSB = 9.4045*10-13 IMAX2 / In_82 A2h
Table 6: Pulse Sources Defined by the PULSE_SRCS Register (1/2)
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MARCH 2008 Value in Pulse Source Register (hex) (dec) 0x10 16 0x11 17 0x12 18 0x13 19 0x14 20 0x15 21 0x16 22 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Name VASQSUM VBSQSUM VCSQSUM WSUM_I WASUM_I WBSUM_I WCSUM_I VARSUM_I VARASUM_I VARBSUM_I VARCSUM_I WSUM_E WASUM_E WBSUM_E WCSUM_E VARSUM_E VARASUM_E VARBSUM_E VARCSUM_E Internal (CE) External (host)
Description The sum of squared voltage samples from each element. LSB = 9.4045*10-13 VMAX2 V2h Imported Energy: W0SUM_I + W1SUM_I + W2SUM_I Imported energy from individual wattmeter elements. Never negative. LSB = 9.4045*10-13 VMAX IMAX / In_8 Wh Imported VARh: VAR0SUM_I + VAR1SUM_I + VAR2SUM_I Exported reactive energy from individual wattmeter elements. Never negative. LSB = 9.4045*10-13 VMAX IMAX / In_8 VARh Exported Energy: W0SUM_E + W1SUM_E + W2SUM_E Exported energy from individual wattmeter elements. Never negative. LSB = 9.4045*10-13 VMAX IMAX / In_8 Wh Exported VARh: VAR0SUM_E + VAR1SUM_E + VAR2SUM_E Exported reactive energy from individual wattmeter elements. Never negative. LSB = 9.4045*10-13 VMAX IMAX / In_8 VARh Connects the pulse generator to the WSUM or VARSUM values internally calculated by the CE. Not selectable for PULSE3 and PULSE4 pulse generators. Indicates that the host will provide values in the APULSER, APULSEW, APULSE3, and APULSE4 registers and that the pulse generator should be updated on the next READY interrupt..
Table 6: Pulse Sources Defined by the PULSE_SRCS Register (2/2)
WRATE (0x2D) This register controls the rate of the pulse generation for the PULSEW, PULSER, PUSE3 and PULSE4 output pins. The inverse pulse rate, expressed as Wh per pulse is:
Kh =
VMAX IMAX 1.5757 Wh / Pulse (X = value formed by PULSE_SLOW and In _ 8 SUM _ CYCLES WRATE X
PULSE_FAST bits in the CONFIG register)
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MARCH 2008 Registers Used for Calibration CAL_IA (0x24), CAL_VA (0x25), CAL_IB (0x26), CAL_VB (0x27), CAL_IC (0x28), CAL_VC (0x29): These registers adjust the gain for the current and voltage measurements of each phase for the purpose of calibration. The calibration factors have to be stored by the host and written to the registers of the 71M6515H after power-up. The allowed range is (215 - 1) to -(215 - 1). The default value of 16384 equals unity gain. If a voltage measurement of phase C is higher than expected, CAL_VC has to be adjusted to: CAL_VC = 16384 / (1 + error) Error must be expressed as a fraction, not a percentage value. If the percent error is +3.5%, the relative error is 0.035, and the calibration factor becomes: CAL_VC = 16384 / (1 + 0.035) = 15829.952, which is rounded up to15830. KVAR (0x2F) This register holds the relative gain of the VAR calculation with respect to the Watt calculation. The value should always be 6444. PHADJ_A (0x2A), PHADJ_B (0x2B), PHAD_C (0x2C) These registers hold the phase correction factors for channels A, B, and C. The values are used by the CE to compensate 15 15 for phase errors induced by current transformers. The allowed range is (2 -1) to -(2 -1). See the Calibration Procedure section for applicable values. If the CE is operated in Rogowski Coil mode, no phase compensation should be required. The default value is not zero and should need to be changed only slightly, if at all. See the Calibration section for details. QUANT_W (0x36), QUANT_VAR (0x37), QUANT_I (0x38) These registers hold DC values that are added to each calculated product in order to compensate for internal quantization (a very small amount) and external noise. These values are normally set to zero. The LSB values for these variable are listed in Table 7. Variable QUANT_W QUANT_VAR QUANT_I LSB Value (VMAX IMAX/ In_8)* 1.04173*10-9 (VMAX IMAX / In_8)* 1.04173*10
2 2 -13 -9
Unit W VAR
(IMAX / In_8 )* 5.08656*10 A (rms) Table 7: LSB Values for QUANT Variables
Nonlinearity is most noticeable at low currents, and can result from input noise and truncation. Nonlinearities can be eliminated using the QUANT_W register. The error can be seen as the presence of a virtual constant noise current that becomes dominant at small load currents. The value to be used for QUANT_W can be determined by the following formula:
error V I In _ 8 QUANT _ W = - 100 VMAX IMAX LSB
Where error = observed error at a given voltage (V) and current (I), VMAX = voltage scaling factor, as described in section Scaling of Measured Values IMAX = current scaling factor, as described in section Scaling of Measured Values LSB = QUANT LSB value = 1.04173*10-9W
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MARCH 2008 Example: For a Wh measurement, an error of +1% was observed at 1A. If VMAX is 600V and IMAX = 208A, and if the measurement was taken at 240V, we determine QUANT_W as follows:
1 240 1 100 QUANT _ W = - = -18460 600 208 1.04173 10 -9
The negative value obtained by the calculation will compensate for the positive error. It does not matter which current value is chosen as long as the corresponding error value is significant (5% error at 0.2A used in the above equation will produce the same result for QUANT_W). Input noise and truncation can cause similar errors in the VAR calculation that can be eliminated using the QUANT_VAR register. VFEED_A (0x44), VFEED_B (0x45), VFEED_C (0x46) These registers hold the compensation factors for feedthrough used for calibrating Rogowski coils. The allowed range is (215-1) to -(215-1). See the section on Rogowski Coil Calibration for details. Registers Controlling Basic Function and Settings of the 71M6515H CONFIG (0x16) The four bytes written to this register determine the basic operation of the 71M6515H. The function of the 28 bits used for this register are explained below: Bit 0: This bit (VAH_SELECT) determines the method used by the post-processor for determining the apparent energy measured in VAh. If the bit is 0 (default), the calculation is based on VRMS, IRMS and the time (t) per the formula: VAh = VRMS * IRMS * t The accuracy of the result can be improved for low currents by setting Bit 0 to 1. The calculation is then based on the Wh and VARh values per the formula:
VAh = Wh 2 + VARh 2
Using the calculation method above, high accuracy can be achieved for low currents. Bit 3: This bit (RTM_EN) enables the Real-Time Monitor function when set to 1.When used, the RTM signal is available at the TMUX pin. Bit 4: This bit (CE_EN) enables the CE when set to 1. The CE has to be enabled for most metering functions. Bits 7-5: These three bits (EQU) define the equation (see table below) to be implemented by the CE. EQU 0 1* 2 3* 4* 5 Watt & VAR Formula VA IA VA(IA-IB)/2 VA IA + VB IB VA (IA - IB)/2 + VC IC VA(IA-IB)/2 + VB(IC-IB)/2) VA IA + VB IB + VC IC Application 1 element, 2W 1o 1 element, 3W 1o 2 element, 3W 3 oDelta 2 element, 4W 3o Delta 2 element, 4W 3o Wye 3 element, 4W 3o Wye
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MARCH 2008 Bits 13-8: These six bits (SUM_CYCLES) define the length of the accumulation interval per the formula:
=
SUM _ CYCLES 42 2520.6
Allowed values are 24 (400ms) through 60 (1000ms), unless the post-processor is disabled. Bit 8 is the LSB. It is important to note that the length of the accumulation interval, as determined by SUM_CYCLES, is not an exact multiple of 1000ms. For example, if SUM_CYCLES = 60, the resulting accumulation interval is:
=
60 42 2520 = = 999.75ms 32768 Hz 2520.62 Hz 13
This means that accurate time measurements should be based on the RTC, not the accumulation interval. Bit 14: This bit (CKOUT_DISB) disables the CKOUT pin when set. The CKOUT pin can be used for diagnostics. For EMC compliance and power saving reasons, CKOUT_DISB should always be set. Bit 15: This bit (ADC_DIS) disables the ADC when set, e.g. to save power. Of course, no metering or measuring can be performed with the ADC disabled. Bits 18-16: These three bits (TMUX) select the source for the TMUX diagnostic output pin. For EMC compliance and power saving reasons, TMUX should be zero (default) if unused. Bit 18 TMUX2 0 0 0 0 1 1 1 1 Bit 17 TMUX1 0 0 1 1 0 0 1 1 Bit 16 TMUX0 0 1 0 1 0 1 0 1 TMUX 0 1 2 3 4 5 6 7 Signal Selected for the TMUX Pin GND MUX_SYNC RTM RTC Output CE_BUSY XFER_BUSY VX_OK (Comparator Output) V3P3/2 =1.5V internal analog voltage
Bits 20-19: These two bits (F_SELECT) select the phase that is to be used for frequency measurement. The frequency will be shown in bits 31-16 of the FREQ_DELTA_T register (and as bit 4 of the STATUS word - in this form as a digitized zero crossing signal). Bit 20 F_SELECT1 0 0 1 1 Bit 19 F_SELECT0 0 1 0 1 F_SELECT 0 1 2 3 Phase Selected Phase A Phase B Phase C Not allowed
Since the signal at the input selected with F_SELECT is used to synchronize filters and other processing stages in the CE, accuracy for most measurements will be reduced if no voltage is present at the selected phase input. Accuracy can be established by selecting the phase that carries a stable signal (A, B, or C). Bit 21: This bit (CE_ONLY) disables the post-processor when set to 1. When the post-processor is disabled, the timeintensive computations of IPHASE, IRMS, VAh and VRMS are not performed, and therefore smaller accumulation times (SUM_CYCLES < 24) are permitted. In this case, the host is responsible for calculating IPHASE, IRMS, VAh and VRMS.
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MARCH 2008 Bits 23-22: These two bits (IMAGE) select the code to be used by the CE. The CE can be operated in standard mode when using CTs and/or shunt resistor sensors or in Rogowski mode when using Rogowski coil sensors. In order to switch the operation mode, the CE has to be disabled first by clearing the CE_EN bit. Bit 23 IMAGE 1 0 0 1 1 Bit 22 IMAGE 0 0 1 0 1 IMAGE 0 1 2 3 CE Code Selected Standard (CT/shunt) Rogowski coil Standard (CT/shunt) Standard (CT/shunt)
Bit 24: This bit (RESET), when reset, forces all internal states of the 71M6515H to their power-up default. Bits 26-25: These two bits (PULSE_SLOW, PULSE_FAST) modify the speed of the pulse generator. PULSE_SLOW and PULSE_FAST determine the factor X in the equation used for Kh as shown in the table below. PULSE_SLOW 0 0 1 1 (default) PULSE_FAST 0 1 0 1 (default) X 1.5*22 = 6 1.5*26 = 96 1.5*2-4 = 0.09375 1.5
PULSE_SLOW and PULSE_FAST will affect the operation of all four pulse outputs. See the Pulse Generation section for details. Bits 29-27: These three bits (IA_8X, IB_8X, IC_8X) apply an additional gain of 8 to the IA, IB, and IC channels when set to 1. This is a useful tool when very small signals are encountered, as is the case when using current shunt resistors with very low resistance while operating at low currents. Care must be taken to avoid clipping. If the input to the meter exceeds IMAX/8, clipping will occur. These bits should normally be zero, unless additional gain following the ADC stage is needed. Bit 30: This bit (DEFAULT_PPM) defines the source of temperature compensation. When DEFAULT_PPM is 1, the 71M6515H will automatically apply compensation coefficients derived from the stored VREF temperature characteristics to the PPMC and PPMC2 registers. When DEFAULT_PPM is zero, the host is allowed to write its own values to the PPMC and PPMC2 registers. STATUS (0x14) The four bytes in this register reflect the status of the various measurement functions of the 71M6515H. This register is read only. When a bit in the STMASK register is set, an interrupt (IRQZ) is generated as soon as the corresponding bit in the STATUS register is set. Bit 0: This bit (BOOTUP) signals a request from the 71M6515H to the host to be initialized. Bit 1: This bit (SAGA ), when set, indicates that the voltage applied to phase A has sagged below SAGTHR. See the for SAG register for a detailed description. Bit 2: This bit (SAGB), when set, indicates that the voltage applied to phase B has sagged below SAGTHR. Bit 3: This bit (SAGC), when set, indicates that the voltage applied to phase C has sagged below SAGTHR. Bit 4: This bit (F0) follows the polarity of the input voltage selected with the F_SELECT bits in the CONFIG register. It represents a smoothed, filtered and squared copy of the fundamental waveform. Bit 5: This bit (MAXV), when set, indicates that a voltage greater than the voltage limit defined in the VI_PTHRESHOLD register had been detected in the previous accumulation interval. Bit 6: This bit (MAXI), when set, indicates that a current greater than the current limit defined in the VI_PTHRESHOLD register had been detected in the previous accumulation interval.
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MARCH 2008 Bit 7: This bit (1SECI, toggles every second. It is controlled by the RTC. Bit 8: This bit (VXEDGE), when set, indicates a change in state of VX comparator. This bit is updated every accumulation interval. Bit 9: This bit (DEDGE), when set, indicates a change in state of any selected DIO pin. This bit is updated every accumulation interval. Pins have to be configured to generate the DEDGE flag using the DIO_INT_CTRL bits in the D_CONFIG register. Bit 10: This bit (XOVF), when set, indicates that the host failed to read at least one of the Wh values. Between interrupts (indicated by the READY bit in the STATUS word), the 71M6515H expects the host to read at least one of the WATTHR_A, WATTHR_B, or WATTHR_C values. Bit 11: This bit (READY), when set, indicates that the 71M6515H has fresh output values ready for the host. Setting this bit in STMASK will enable the hardware interrupt output pin IRQZ. Bit 14-12: These bits (bit 12 for phase A, bit 13 for phase B, bit 14 for phase C), when set, indicate that the energy received from element A, B, or C is below the creep threshold defined in the CREEP_THRSHLD register or that the current in elements A, B, or C is below the threshold defined in bits 15-0 of the START_THRESHLD register. The creep condition flagged by bits 14-12 of the STATUS register indicates that Wh, VARh, and IRMS measurements of element A, B, or C have been zeroed out. Consequently, accumulation did not occur. Bit 15: This bit (CMD_IGNORED), when set, indicates that the 71M6515H ignored the last command received from the host. The reason can be any type of command incompatibility, e.g. attempts to write to a read-only register. Bit 16: This bit (PULSEW_ERR), when set, indicates that the pulse generator PULSEW is configured for external (host) input, but did not receive an update during the previous accumulation interval. Bit 17: This bit (PULSER_ERR), when set, indicates that the pulse generator PULSER is configured for external (host) input, but did not receive an update during the previous accumulation interval. Bit 18: This bit (PULSE3_ERR), when set, indicates that the pulse generator PULSE3 is configured for external (host) input, but did not receive an update during the previous accumulation interval. Bit 19: This bit (PULSE4_ERR), when set, indicates that the pulse generator PULSE4 is configured for external (host) input, but did not receive an update during the previous accumulation interval. STMASK (0x15) The four bytes in this register enable interrupts when the corresponding bit in the STATUS register is set. The default value for STMASK is zero. When a bit in the STMASK register is set, an interrupt (IRQZ) is generated as soon as the corresponding bit in the STATUS register is set. Interrupts indicated by IRQZ do not necessarily have to be synchronized with accumulation intervals. For example, the toggling of a signal applied to the DIO pins (D0...D7), when the interrupt is enabled with the DIO_INT_CTRL register, can cause an interrupt at any time.
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MARCH 2008 Registers Controlling Temperature Measurement and Compensation DEG_SCALE (0x1C) This register holds the scale factor used to calculate the internal temperature value provided by the temperature sensor to temperature in degrees Celsius (C). The default value is 22721 and should not be changed. FREQ_DELTA_T (0x11) This register holds frequency and temperature information in two bytes each. 31 FREQUENCY (see Output Registers) 16 15 DELTA_T 0
Bits 15-0: These bits (DELTA_T) represent the temperature information relative to the value stored in the TEMP_NOM register. One LSB is equivalent to 0.1C. The formula used for DELTA_T is: DELTA_T = -DEGSCALE*2-22*(TEMP_RAW-TEMP_NOM) TEMP_NOM (0x13) This register holds the nominal (reference) temperature. During calibration, the host must write the value read from TEMP_RAW to TEMP_NOM in order to enable temperature compensation. See the Meter Calibration section for details. The temperature available in register DELTA_T is based on the difference between the current temperature, as provided in TEMP_RAW, and the reference temperature provided by TEMP_NOM. TEMP_RAW (0x12) This read-only register holds the raw temperature provided by the temperature sensor on the 71M6515H chip. During calibration, the host must write the value read from TEMP_RAW to TEMP_NOM in order to enable temperature compensation. Example: At calibration time, the raw temperature value of 853030 was read from the TEMP_RAW register and written to the TEMP_NOM register. At a later time, the raw temperature register reads 844866. The 71M6515H calculates the temperature difference to: DELTA_T = -DEGSCALE*2-22*(TEMP_RAW-TEMP_NOM) = 44 This value is interpreted as +4.4C.
PPMC1_2 (0x1B) This register holds the linear and squared compensation factors for the ADC temperature compensation. The allowed range is (215 - 1) to - (215 - 1). Both words are reset to zero if TEMP_NOM equals zero. 31 PPMC = ADC linear factor (PPMC = 26.84 * PPM/C ) 16 15 0 PPMC2 = ADC quadratic factor (PPMC2 = 1374 * PPM/C2)
Changes to PPMC1_2 by the host are only allowed if the DEFAULT_PPM bit in the CONFIG register is zero. If additional temperature compensation by the host, e.g. for external components, is required, the procedure is as follows: 1) 2) The host sets the DEFAULT_PPM bit in the CONFIG register to 1 and then reads PPMC and PPMC2. The host then adds the compensation factors to PPMC and PPMC2, resets the DEFAULT_PPM bit in the CONFIG register to 0 and then writes the modified values to PPMC and PPMC2.
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MARCH 2008 Y_DEG0 (0x18) This register holds the constant compensation factor for the RTC temperature compensation. One LSB is equivalent to 0.1PPM. Bits 31-16: These bits (Y_CALC0) represent the constant compensation factor. Y_DEG1_2 (0x19) This register holds the linear and quadratic compensation factors for the RTC temperature compensation. 31 16 15 0
Y_CALC1 = linear compensation factor. One LSB is equivalent to 0.01PPM/
Y_CALC2 = quadratic compensation factor. One LSB is equivalent to 0.001PPM/C
Both Y_DEG0 and Y_DEG1_2 can be used to compensate the RTC to be accurate over the whole temperature range by characterizing the crystal. Registers for Output Signals PULSEW_R_CNTS (0x41) This register contains the pulse count for the PULSEW and PULSER output pins for the past accumulation interval. The counters will be cleared at the beginning of each accumulation interval and then start counting up with each generated pulse. Bit 15-0: The counter for the PULSER (VARh) generator. Bit 31-16: The counter for the PULSEW (Wh) generator. 31 Counter for the PULSEW generator (Wh) 16 15 Counter for the PULSER generator (VARh) 0
At pulse rates that do not result in generation of whole counts per accumulation interval, e.g. 3 1/3 pulses, the count equivalent to the next lower natural number will be generated until the residue accumulates to a full count, i.e. the pulse sequence generated will be 3, 3, 3, 4, 3, 3, 3, 4... PULSE3_4_CNTS (0x42) This register contains the pulse count for the PULSE3 and PULSE4 output pins for the accumulation interval. The counters will be cleared at the beginning of each accumulation interval and then start counting up with each generated pulse. Bit 15-0: The counter for the PULSE4 generator. Bit 31-16: The counter for the PULSE3 generator. 31 Counter for the PULSE3 generator IASQSUM (0x39), IBSQSUM (0x3A), ICSQSUM (0x3B) These registers hold the sum of the squared current samples collected during the previous accumulation interval. The values for IASQSUM, IBSQSUM, and ICSQSUM are provided directly by the CE and are not post-processed. The magnitude of the accumulated samples is determined by: 16 15 Counter for the PULSE4 generator 0
LSB =
IMAX 2 9.4045 10 -13 A 2 h 2 In _ 8
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MARCH 2008 IASQFRACT (0x4A), IBSQFRACT (0x4B), ICSQFRACT (0x4C) These read-only registers hold the difference between the 10-bit residual squared current sum of the current accumulation interval and the 10-bit residual squared current sum of the previous interval. If IASQSUM, IBSQSUM, or ICSQSUM are used to calculate current, the value obtained over several accumulation intervals will be accurate due to averaging, but the individual values will have a higher uncertainty than when using IASQFRACT, IBSQFRACT, and ICSQFRACT. The most accurate calculation of the squared current for a phase X (IXSQ) uses the formula: IXSQ = IXSQSUM + 2-10 IXSQFRACT INSQFRACT (0x4D) This register holds the difference between the 10-bit residual squared neutral currents of the current accumulation interval and the 10-bit residual squared neutral currents of the previous interval. The value can be used to improve the accuracy of the squared neutral current reading by applying the formula: INSQ = INSQSUM + 2-10 INSQFRACT INSQSUM (0x3C) This register holds the sum of the square of the calculated neutral current collected during the previous accumulation interval. The calculation is implementing the following equation:
INSQSUM = (I 0 + I1 + I 2)
2
The magnitude of the accumulated samples is determined by:
LSB =
IMAX 2 9.4045 10 -13 A 2 h 2 In _ 8
IPHASE_ABC (0x0F) This register holds voltage-to-current phase information for all three phases. Positive phase means lagging current (inductive load). One LSB is equivalent to 1 degree. The range is from (28 - 1) to -(28 - 1). Since the phase calculation involves the post-processor, these registers will not be functional when the CE_ONLY bit in the CONFIG register is set. Bits 8-0: These bits (IPHASE_C) represent the voltage-to-current phase angle in phase C. Bits 17-9: These bits (IPHASE_B) represent the voltage-to-current phase angle in phase B. Bits 26-18: These bits (IPHASE_A) represent the voltage-to-current phase angle in phase A. IRMS_A (0x0C), IRMS_B (0x0D), IRMS_C (0x0E) These registers hold the post-processed RMS current for each phase. Only the 16 most significant bits are used. The magnitude of the values is determined by:
LSB =
6.8781 10 -9 IMAX In _ 8 SUM _ CYCLES
A rms
Since the RMS calculation involves the post-processor, these registers will not be functional when the CE_ONLY bit in the CONFIG register is set. If higher precision is required, the host must calculate the RMS currents from the values in the IASQSUM, IBSQSUM, and ICSQSUM registers. For even higher precision, the IASQFRACT, IBSQFRACT, ICSQFRACT registers should be used.
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MARCH 2008 Example: The register IRMS_C reads the value 2,079,670. Assuming IMAX to be 208A, and using the formula above, we determine the RMS current of phase C to:
I RMS = 2079670
6.8781 10 -9 208 60
= 0.0385 A
VASQSUM (0x3D), VBSQSUM (0x3E), VCSQSUM (0x3F) These registers hold the sum of the squared voltage samples collected during the previous accumulation interval. The values for VASQSUM, VBSQSUM, and VCSQSUM are provided directly by the CE and are not post-processed. The magnitude of the accumulated samples is determined by:
LSB = VMAX 2 9.4045 10 -13 V 2 h
VAH_A (0x06), VAH_B (0x07), VAH_C (0x08) These registers hold the apparent energy collected during the previous accumulation interval. The magnitude of the accumulated samples is determined by:
LSB = 9.4045 10 -13
VMAX IMAX In _ 8
VAh
Since the VAh calculation involves the post-processor, these registers will not be functional when the CE_ONLY bit in the CONFIG register is set. VARH_A (0x03), VARH_B (0x04), VARH_C (0x05) These registers hold the reactive energy collected during the previous accumulation interval. The magnitude of the accumulated samples is determined by:
LSB = 9.4045 10-13
VPHASE_ABC (0x10)
VMAX IMAX In _ 8
VARh
This register holds the phase angle between the voltages of phases A/C and A/B. The LSB is one degree. Bits 15-0: These bits (VPHASE_AC) hold the phase angle between VA and VC. Bits 31-16: These bits (VPHASE_AB) hold the phase angle between VA and VB. VRMS_A (0x09), VRMS_B (0x0A), VRMS_C (0x0B) These registers hold the post-processed RMS voltage for each phase. Only the 16 most significant bits are used. The magnitude of the values is determined by:
LSB =
6.8781 10 -9 VMAX SUM _ CYCLES
V rms
Since the RMS calculation involves the post-processor, these registers will not be functional when the CE_ONLY bit in the CONFIG register is set. If higher precision is required, the host must calculate the RMS voltages from the values in the VASQSUM, VBSQSUM, and VCSQSUM registers. Example: The register VRMS_B reads the value 425,778,000. Assuming VMAX to be 600V, and using the formula above, we determine the RMS voltage of phase B to:
V RMS = 425778000
6.8781 10 -9 600 60
= 226.85V
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MARCH 2008 WH_A (0x00), WH_B (0x01), WH_C (0x02) These registers hold the real energy collected during the previous accumulation interval. The magnitude of the values is determined by:
LSB = 9.4045 10 -13
VMAX IMAX In _ 8
Wh
Example: The register WH_A reads the value 236,675 for one accumulation interval of one second. Assuming 600V for VMAX, 208A for IMAX, and unity gain, we determine the real energy to be: E = 236,675*600*208*9.4045*10-13 Wh = 0.0277781Wh. By multiplying with 3,600, we get 100Wh/h, which means the applied power is 100W. FREQ_DELTA_T (0x11) This register holds frequency and temperature information in two bytes each. Bits 31-16: These bits (FREQUENCY) represent the frequency of the input signal selected with the F_SELECT bit of the CONFIG register. One LSB is equivalent to 0.1Hz. MAIN_EDGE_CNT (0x35) This register holds the number of zero crossings of the input phase selected by the F_SELECT bits in the CONFIG register detected in the previous accumulation interval. The value in MAIN_EDGE_CNT can be used by the host to correct its own RTC or to synchronize events to the line voltage. Registers Controlling Alarms and Thresholds CREEP_THRSLD (0x1D) The four bytes written to this register determine the creep threshold. Setting a creep threshold helps suppressing I2H, Wh and VARh readings when the values of WSUM and VARSUM are determined to be below the creep threshold. Example: The creep threshold of a meter operating with an accumulation interval of 1000ms is to be configured to be 15mA at 240V. The meter is using a VMAX of 600V, an IMAX of 208A, and is not using the additional gain of 8. The numerical value for the CREEP_THRSLD register is to be determined. With 15mA, the power per phase will be 3.6W, or 0.001Wh per second. With the LSB of WSUM readings given as 9.4045*10-13*VMAX*IMAX [Wh], we determine the value to:
-13 n = 0.001Wh / (9.4045*10 *VMAX*IMAX /In_8 Wh) = 8520.2
The rounded down value of 8520 is written to the CREEP_THRSLD register. SAG (0x2E) This register holds the voltage and timing threshold for sag detection. Bits 15-0: These bits (SAG_CNT) hold the sag count. A sag condition must persist for at least SAG_CNT samples before a 15 sag alarm is generated. The allowed range is 1 to (2 -1), and the default is 80 (31.7ms). The time period defined by SAG_CNT is: T = SAG_CNT*397s Bits 31-16: These bits (SAGTHR) hold the voltage threshold that is to be applied for sag detection. The peak voltage must exceed SAGTHR once each SAG_CNT samples in order to prevent a SAG warning. One LSB is defined as:
LSB = 7.8798 2 16 10 -9 VMAX
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MARCH 2008 Example: A meter operating at 50Hz and 240V (RMS) is supposed to apply a sag threshold of 180V (RMS) for at least four periods before a sag warning is issued. VMAX is 600V. Which values are to be selected for SAG? Four periods translate to T = 4 * 20ms = 80ms. This means that SAG_CNT = T/397s = 202. 180V (RMS) translate to 255V (peak), so SAGTHR is determined by
SAGTHR =
START_THRESHLD (0x40)
255 255 = = 823 LSB 7.8798 2 16 10 - 9 600
This register holds the voltage and current thresholds that apply to the calculation of frequency, zero crossings, voltage phase and energy values. If the current is below the value stored in I_START, calculation of RMS current, and energy (Wh, VARh and VAh) is suppressed. Bits 15-0: These bits (I_START) hold the threshold to be applied for under-current. If ISQSUM< I_START, all postprocessed values are set to zero for that phase. This includes reported values for Wh, VARh, VAh, IRMS, VPHASE, IPHASE, PULSER, PULSEW, PULSE3 and PULSE4. This applies only if CREEP_THRSLD is not set to zero. One LSB is defined as:
LSB =
IMAX 2 9.4045 10 -13 A 2 h In _ 8
Elements with ISQSUM< I_START will set the creep bits in the STATUS register. Bits 31-16: These bits (V_START). hold the threshold to be applied for under-voltage. If VRMSLSB = VMAX 2 2 16 9.4045 10 -13 V 2 h
Elements with VRMS< V_START will not set the creep bits in the STATUS register. VI_PTHRESHOLD (0x17) This register holds the threshold for over-voltage and over-current alarms. Bits 15-0: These bits (I_PTHRESHOLD) hold the threshold to applied for over-current alarm. The threshold comparison is applied to the upper 16 bits of the values in IRMS: One LSB is defined as:
LSB =
450 .76 10 -6 IMAX In _ 8 SUM _ CYCLES
A rms
Bits 31-16: These bits (V_PTHRESHOLD). hold the threshold to applied for over-voltage alarm. The threshold comparison is applied to the upper 16 bits of the values in VRMS One LSB is defined as:
LSB =
450 .76 10 -6 VMAX SUM _ CYCLES
V rms
Example: A meter designed with VMAX=600V and IMAX=208A is supposed to apply an overvoltage threshold of 520V (RMS) and an over-current threshold of 400A (RMS). Which values are to be selected for V_PTHRESHOLD and I_PTHRESHOLD?
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V _ PTHRESHOLD =
520 520 = = 14,893 LSB 450.76 10 - 6 600 SUM _ CYCLES
I _ PTHRESHOLD =
400 400 = = 33,046 LSB 450.76 10 -6 208 SUM _ CYCLES
Registers Controlling Time and RTC Functions OP_TIME (0x1E) This register holds the operating time expressed in 1/100 hours. The register will be reset to zero whenever the host writes time or date to the RTC. RTC_DATE (0x20) This register holds the date information provided by the RTC. The register can be written to in order to set the date. Bits 15-8: These bits contain the year information (0 to 255). The value 0 represents the year 2000. Bits 23-16: These bits contain the month information (01 to 12). The value 01 represents January. Bits 31-24: These bits contain the day of month information (01 to 31). RTC_TIME_DAY (0x1F) This register holds the time and day information provided by the RTC. The register can be written to in order to set the time. Bits 7-0: These bits contain the day of the week (01 to 07). The value 01 represents Sunday. Bits 15-8: These bits contain the hour information (00 to 23). The value 00 represents midnight. Bits 23-16: These bits contain the minutes information (00 to 59). Bits 31-24: These bits contain the seconds information (00 to 59). Example: The value 200835 is read from the OP_TIME register. This means that the meter has been running since the last reset or power-up for t = 800850/100h = 8008.50h or 8,008h and 30 minutes (333.6875 days or 333 days and 16.5h).
Registers Used for Test Functions RTM (0x21) This register controls the Real-Time Monitor. When the RTM_EN bit in the CONFIG register is set, the values of CE RAM locations specified with the RTM register can be routed to the TMUX pin as a serial data stream. The TMUX bits in the CONFIG register must be set to 3 in order to select the RTM output for the TMUX pin. Bits 7-0: These bits (RTM3) select the CE address for RTM3. Bits 15-8:. These bits (RTM2) select the CE address for RTM2. Bits 23-16: These bits (RTM1) select the CE address for RTM1. Bits 31-24: These bits (RTM0) select the CE address for RTM0.
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MARCH 2008 SSI (0x22) This register controls the function of the Serial Synchronous Interface (SSI). The function of the SSI is described in the Internal Resources section of this data sheet. If the SSI is enabled (bit 23, SSI_EN, in the SSI register), a block of CNT words starting at the address BEG will be transmitted each 397s. Bits 7-0: These bits (CNT) select the number of CE RAM address locations to be transmitted. The value in CNT must be >= 0. Bits 15-8: These bits (BEG) define the start address of the transfer region of the CE data RAM address. Bit 16: This bit must be set to zero. Bit 17: This bit must be set to zero. Bit 18: This bit (SSI_FPOL) defines the polarity of the SFR pulse signal (0: positive, 1: negative). Bits 20-19: These bits (SSI_FSIZE) define the frame pulse format as follows: Bit 20 0 0 1 1 Bit 19 0 1 0 1 SSI_FSIZE 0 1 2 3 SSI Frame Pulse Format Once at beginning of SSI sequence Every 8 bits Every 16 bits Every 32 bits
Bit 21: This bit (SSI_CGATE) enables the clock to be gated. When low, the SSCLK signal is active continuously, when high, the SSCLK signal is held low when no data is being transferred. Bit 22: This bit (SSI_10M) defines the speed of the SSCLK signal: 0: 5MHz, 1: 10MHz. Bit 23: This bit (SSI_EN), when set to 1, enables the SSI interface. Registers Used for I/O Control D_CONFIG (0x1A) This register holds three bytes that are used to manipulate the DIO pins of the 71M6515H. Bits 7-0: These bits (DIO_VALUE) form the data register for the DIO pins D0 through D7. When a byte is written to DIO_VALUE, the pins configured as outputs (using the D_DIR register) will change their state accordingly. Pins configured as inputs will ignore the byte written to DIO_VALUE. Reading DIO_VALUE will return a byte that reflects the state of all pins regardless whether they are configured as inputs or outputs. Bits 15-8: These bits are not used Bits 23-16: These bits (D_DIR) define the data direction. Bit 0 controls the D0 pin, bit 7 controls the D7 pin. Setting the bit corresponding to a pin to 1 makes the pin an output, clearing it to 0 makes it an input. Bits 31-24: These bits (DIO_INT_CTRL) form a mask enabling the DEDGE interrupt (bit 9 of the STATUS word register). Bit 8 controls the D0 pin, bit 15 controls the D7 pin. Setting the bit corresponding to a pin to 1 enables the DEDGE interrupt, clearing the bit disables the interrupt. If the bit in DIO_INT_CTRL is set and a transition from high to low or from low to high occurs, the DEDGE interrupt bit in the STATUS word register will be set in the following accumulation interval.
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MARCH 2008 Example: DIO pins D0 through D3 are to be configured as outputs, while D4 through D7 are to be inputs. DIO7 must generate a DEDGE interrupt when the input value changes, and D0 through D3 must apply the hexadecimal pattern 0x05. This makes the selection for the D_CONFIG registers as follows: DIO_INTCTRL = 0x80, D_DIR = 0x0F, DIO_VALUE = 0x05 The values are combined into the 32-bit pattern 0x800F0005. Example: D0 through D5 are to be configured as outputs, while D6 and D7 are to be inputs. D6 and D7 must generate a DEDGE interrupt when their input value changes. This makes the selection for the D_CONFIG registers as follows: DIO_INTCTRL = 0xC0, D_DIR = 0x3F The values are combined into the 32-bit pattern 0xC03F0000.
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MARCH 2008 Registers in Numerical Order Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F Name WH_A WH_B WH_C VARH_A VARH_B VARH_C VAH_A VAH_B VAH_C VRMS_A VRMS_B VRMS_C IRMS_A IRMS_B IRMS_C IPHASE_ABC VPHASE_ABC FREQ_DELTA_T TEMP_RAW TEMP_NOM STATUS STMASK CONFIG VI_PTHRESH Y_DEG0 Y_DEG1_2 D_CONFIG PPMC1_2 DEG_SCALE CREEP_THRSLD OP_TIME RTC_TIME_DAY Address 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F Name RTC_DATE RTM SSI RESERVED CAL_IA CAL_VA CAL_IB CAL_VB CAL_IC CAL_VC PHADJ_A PHADJ_B PHADJ_C WRATE SAG KVAR APULSEW APULSER APULSE3 APULSE4 PULSE_WIDTH MAIN_EDGE_CNT QUANT_W QUANT_VAR QUANT_I IASQSUM IBSQSUM ICSQSUM INSQSUM VASQSUM VBSQSUM VCSQSUM 0x60 0x61 0x62 0x63 0x64 0x65 CE_PROG_ADDR CE_DATA_ADDR CE_PROG CE_DATA CE_PROG_INC CE_DATA_INC Address 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E IASQFRACT IBSQFTACT ICSQFRACT INSQFRACT GAIN_ADJ Name START_THRESHLD PULSEW_R_CNTS PULSE3_4_CNTS PULSE_SRCS VFEED_A VFEED_B VFEED_C
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MARCH 2008 APPLICATION INFORMATION Meter Circuits Bits 7 through 5 (EQU) of the CONFIG register allow the selection of the metering equation that is to be implemented by the 71M6515H. The equation to be used depends on the meter configuration. Figure 16 shows how the 71M6515H is connected for the most common configuration, the three-phase, four-wire WYE. The neutral wire connects to V3P3A. For this configuration, equation 5 must be selected.
Distribution transformers
A
CT
LOAD A
B
CT
LOAD B
C N
CT
LOAD C
71M6515H
IA IB IC V3P3A VA VB VC
ANSI: Form 16S EQU = 5
P=VA*IA+VB*IB+VC*IC
Figure 16: 4-Wire 3-Phase WYE Connection In many three-phase three-wire configurations, one phase can be grounded, as shown in Figure 17. Again, the grounded wire is connected to V3P3A. For this configuration, equation 2 must be selected. The four-wire three-phase delta configuration is shown in Figure 20. In this case, the center tap of the transformer that provides the A-C voltage is grounded. the grounded wire is connected to V3P3A. For this configuration, equation 2 must be selected. For this configuration, equation 3 must be selected, i.e. P = VA*(IA-IB)/2 + VC*IC.
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B
LOAD B
C
A
LOAD A
IA IB IC V3P3A VC VA VB
EQU = 2 P=VA*IA+VB*IB 71M6515H
Figure 17: 3-Wire 3-Phase Delta Connection
C
LOAD C
B NEUTRAL A
LOAD B
LOAD A
IA IB IC V3P3A VC VA VB
71M6515H
Figure 18: 4-Wire 3-Phase Delta Connection
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MARCH 2008 Communication between the 71M6515H and the Host Processor General To ensure proper transfer of energy and other values from the 71M6515H to the host, the output data of the 71M6515H must be read by the host each time they are ready, and no energy-related datum can be missed. This requires close synchronization between the 71M6515H and the host. Control Signals Figure 19 shows the control signals between the 71M6515H and the host processor. These signals are: 1) 2) 3) 4) 5) 6) 7) TX: Serial transmit output pin of the 71M6515H RX: Serial receive input pin of the 71M6515H IRQZ: Interrupt output, used as "Data Ready" hardware signal of the 71M6515H (low-active) RESETZ: Reset input pin of the 71M6515H (low-active, should be pulled up to V3P3) UARTCSZ: UART reset input pin of the 71M6515H (low-active) BAUD_RATE: Baud rate select input pin of the 71M6515H (optional) PULSE_INIT: Pulse polarity select input pin of the 71M6515H (optional)
TX and RX are the most essential signals for the communication between the 71M6515H and the host processor. The IRQZ pin provides a useful output signal that can be used by the host to determine whether the 71M6515H has fresh data ready. IRQZ can be connected to either an interrupt input or general I/O input of the host processor. RESETZ can be used to force a hardware reset of the 71M6515H, and UARTCSZ can be used to reset (purge) the UART of the 71M6515H communication buffers for reconfiguration. The additional pins BAUD_RATE and PULSE_INIT can be hardwired for configuring the communication baud rate and the pulse status, or controlled on power up by the host processor.
71M6515H Host
T X RX IRQZ
3.3V
RX T X IRQ or DIO_1
DIO
DIO0...DIO7 RESETZ UARTCSZ BAUD_RATE PULSE_INIT DIO_2 DIO_3 DIO_4 DIO_5
Figure 19: Connections between 71M6515H and Host Note that the DIO pins of the host processor used to control the 71M6515H are not lost, since the 71M6515H can provide eight DIO pins ((DIO0...DIO7) to act as general-purpose DIO pins. Since the communication between the 71M6515H and its host is based on a binary protocol, it is imperative for the host to issue a clean character stream without added bytes (UART drivers of high-level operating systems often add extra bytes to the character stream, relying on error-detecting protocols). In case the 71M6515H loses synchronization due to unexpected bytes sent by the host, it times out after 10ms (maximum 20ms). The 71M6515H flags a time-out condition by setting the BOOTUP flag in the STATUS register. This happens because the incomplete or garbled data could have included a write command to the CONFIG register or other important registers.
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71M6515H Energy Meter IC
DATA SHEET
MARCH 2008 Methods of Control Two different methods of control can be used by the host processor: 1) Synchronization using the IRQZ pin of the 71M6515H (interrupt or DIO pin polling method, see Figure 20): a. Interrupt Method: The IRQZ pin of the 71M6515H is connected to a pin of the host processor that can generate an interrupt for the host processor. This is the easiest method for synchronization between the 71M6515H and the host. The CONFIG register of the 71M6515H is set up to generate an interrupt on the IRQZ pin whenever fresh data are ready, and the interrupt service routine of the host processor reads the fresh data out of the 71M6515H. b. DIO pin polling method: The IRQZ pin of the 71M6515H is connected to a DIO pin of the host processor. The host processor polls the status of the DIO pin as frequently as possible or through a timer-based polling method. The CONFIG register of the 71M6515H is set up to have the IRQZ pin to go low on every fresh data ready status, and the timer-serviced polling of the host processor will monitor the status of the DIO pin and initiate the serial communication when IRQZ is detected. For this method to be effective, the firmware of the host processor must maintain the timer interrupt to be the highest priority, followed by the serial communications priority. 2) Polling the READY bit in the STATUS word of the 71M6515H (status polling method, see Figure 21). This method requires that the host processor utilizes a timer with 1ms to 5ms resolution tied into the highest-priority interrupt. The interrupt service routine must initiate reading the STATUS register, preferably at least every 10ms, in order to monitor the READY bit, but the host processor must wait for the response of each status request. Otherwise, the STATUS register read operations will be stacked in the 71M6515H resulting in multiple responses. If a delayed response is received upon a STATUS register read, the host processor will know that the 71M6515H is within its post-processing period, which makes it necessary hat the host waits for the response. Every time the READY bit in the STATUS register is not set, indicating that data is not available, the host should poll again
read command from host read command from host
6515H data
6515H data
IRQZ
post-processor active 80ms
post-processor active 80ms
time 500ms
200ms
300ms
400ms
Figure 20: Timing Diagram (Using IRQZ, SUM_CYCLES = 12) The communication between the 71M6515H and the host processor can always be reset without disturbing the metering function by utilizing the UARTCSZ and BAUDRATE pins. Configuring the BAUDRATE pin without resetting the UART buffers is not recommended. The UART of the 71M6515H can be "reset" by pulling the UARTCSZ pin low. This will force the UART back into the default configuration while clearing all buffers (UART buffers, UART-related buffers in the firmware).
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
V1.4
71M6515H Energy Meter IC
DATA SHEET
MARCH 2008
read commands from host read commands from host
6515H not ready 6515H data
6515H not ready
6515H data
post-processor active 330ms
post-processor active 330ms
time
1000ms
2000ms
Figure 21: Timing Diagram (Host Polling) Communication Steps for Interrupt Method: The following is a list of commands required from the host processor to establish communication with the 71M6515H. 1) 2) 3) Establish host baud rate and data format as required by the 71M6515H. Configure the DIO pins (D0...D7), if required, using the D_CONFIG register Configure the 71M6515H by selecting the CE image (bits 23-22), equation (bits 7-5), pulse rate (bits 26-25), followed by enabling the CE (bit 4 in the CONFIG register). The bit pattern sent to CONFIG should have all bits set to their default state, as given in the Register Table. Write the TEMP_RAW value obtained at calibration into the TEM_NOM register to enable temperature compensation. Write the calibration coefficients into registers CAL_IA, CAL_VA, CAL_IB, CAL_VB, CAL_C, CAL_VC, PHADJ_A, PHADJ_B, PHADJ_C. Write calibration values to the VFEED_A/B/C registers if the Rogowski image is used. Configure WRATE with the value required to generate the desired pulse rate. Establish creep, sag and over/under voltage/current thresholds, if necessary, by writing values to the CREEP_THRSLD, SAG, VI_PTHRESH, and VI_THRSHLD registers. Set the READY bit in the status mask STMASK in order to enable the generation of interrupts on the IRQZ pin. Read at least one accumulated value register (WATTH_X, or VAH_X, or VARH_X).
4) 5) 6) 7) 8) 9)
10) Wait for the IRQZ pin to go low. 11) After receiving the interrupt, read at least one accumulated value register (WATTH_X, or VAH_X, or VARH_X) in order to maintain interrupt generation. Read the bits in the STATUS word to detect potential faults (overflow signaled by the XOVF flag or uninitialized condition signaled by the BOOTUP flag) or warnings and events (sag, creep, excessive voltage or current, DIO signal changes). If necessary, take corrective action. 12) After reading the required data from the 71M6515H, configuration changes should be made, if necessary. These configuration changes should be completed before the pre-processing period begins again.
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
V1.4
71M6515H Energy Meter IC
DATA SHEET
MARCH 2008 Timing The fundamental factor for all timing considerations is SUM_CYCLES, which determines the length of the accumulation interval for the 71M6515H per the equation:
=
SUM _ CYCLES 42 2520.6 Hz
The default setting for SUM_CYCLES is 60, which yields an accumulation interval close to 1,000ms. A conservative minimum number for SUM_CYCLES is 24, which yields an accumulation interval close to 400ms. Both calculations by the post-processor in the 71M6515H and the communication between 71M6515H and the host have to be completed within the accumulation interval. If an accumulation interval has passed, and the energy values have not been read by the host, they are lost forever. In order to analyze the timing of the communication between the 71M6515H and the host, it is useful to know the basic timing requirements of the post-processor of the 71M6515H. Some timing parameters are listed in Table 8. CE_ONLY Disabled Disabled Enabled VAh Calculation Vector method: Resulting Calculation Time 350ms 80ms 40ms
VAh = Wh 2 + VARh 2
Vrms*Irms method X Table 8: Post-processor Timing
As can be seen in Table 8, the calculation time can be greatly reduced if the VAh values are calculated using the method of multiplying Vrms by Irms (by resetting bit 0 in the CONFIG register), which is less accurate at low currents. Further improvement can be achieved by disabling the post-processor using the CE_ONLY bit in the CONFIG register. This is possible for applications where the registers IPHASE, IRMS, VAh and VRMS are not required. It becomes clear now that the minimum value of 24 for SUM_CYCLES, equivalent to a 400ms accumulation interval, accommodates the worst-case scenario, using the vector method, which requires 350ms post-processing time. This setting leaves around 50ms for the communication to take place between the 71M6515 and the host. If the simpler Irms*Vrms method is chosen for VAh, a lower value can be selected for SUM_CYCLES. Lower values for SUM_CYCLES, for example 12, yielding a 200ms accumulation interval, are possible, leaving still 120ms for host communications, as long as the Vrms*Irms method for VAh is used. Some other timing parameters are listed in Table 9. Parameter Time from power-up to UART being functional Time from HW reset to UART being functional Time from soft reset to UART being functional Value 370ms 10% 370ms 10% 245ms 10% Soft reset = RESET bit in CONFIG register is set high. UARTCSZ is polled just before the 71M6515H checks its data buffer for a command. This means that the command latency specified in the Electrical Specifications section also applies to the UARTCSZ pin. Comment
Time from UARTCSZ pin low to UART being functional
20ms
Table 9: UART Timing Parameters
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
V1.4
71M6515H Energy Meter IC
DATA SHEET
MARCH 2008 PACKAGE OUTLINE
11.7 12.3
11.7 12.3
PIN No. 1 Indicator 9.8 10.2 0.00 0.20
+
0.60 Typ.
0.50 Typ.
0.14 0.28
1.40 1.60
NOTE: Controlling dimensions are in mm Ordering Information PART DESCRIPTION 71M6515H 64-Pin LQFP Lead-Free, 0.1% accuracy 71M6515H 64-Pin LQFP Lead-Free, 0.1% accuracy, T&R ORDER NO. 71M6515H-IGT/F 71M6515H-IGTR/F PACKAGING MARK 71M6515H-IGT 71M6515H-IGT
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
V1.4
71M6515H Energy Meter IC
DATA SHEET
MARCH 2008 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Date October 26, 2005 December 11, 2006 Description First publication. Changed capacitor values for XIN/XOUT Corrected addresses for CE_DATA and made addresses CE_DATA etc. visible in table "Registers in Numerical Order". Changed frequency range to 46-64Hz and "Real-time clock for TOU" to "Real-time clock with temperature compensation" on title page. Added complete chapter on communication between host and 6515H. Changed pin name V1 to VFLT in Electrical Specification. Consolidated spelling for CREEP_THRSLD register. Added explanation for X in formula for WRATE. Added information on processing time for registers involving post-processing. Changed default value for WRATE to 683. Deleted note on low-pass filter in the CE in CONFIG register description. Added note at CONFIG register description stating that phase with stable voltage can be selected with F_SELECT to avoid inaccurate measurements and note stating that PULSE_SLOW and PULSE_FAST affect all four pulse sources. Added diagram "Connections between 71M6515H and host". Added I/O Equivalent Circuit diagrams and circuit type numbers in Pin Descriptions. Added note in Pin Descriptions stating that the voltage at RX must not exceed 3.6V. Added VREF aging data. Clarified polarity of SSDAT and SSCLK pins. Changed recommended value for capacitors at XIN/XOUT to 22pF. Changed recommended crystal to ECS ECX-3TA series. Added note on exact length of default accumulation interval. Corrected bit locations for D_CONFIG register. Added note in pin description for D0-D7 and Digital I/O" section: D0 through D7 float after reset or power-up and are configured as outputs and driven low 140ms after RESETZ goes high. Updated default values for VIPTHRESH and VI_THRESH. Changed pin and register names to PULSEW and PULSER and updated block diagram (Figure 2), updated pin-out diagram with corrected pin names. Removed COMPARATOR table in ELECTRICAL SPECIFICATIONS. Changed note for SRDY in pin description table to "SRDY should be tied to ground", deleted Figure 13 (SRDY function) and removed all text describing the function of SRDY (except that SRDY should be grounded), deleted Figure 13 (SSI Timing w/ SRDY) and removed references to SRDY in Figure 12. Consolidated spelling of Y_CALC etc. constants in section "Temperature Compensation for the Crystal and RTC" and in the register tables. Added reference to fast calibration procedure (AN_651X_022). Added diagrams for metering configurations. Improved Table 6 and explanation of PULSE_SRC register. Changed capacitor values for XIN/XOUT to 27pF and added recommended load capacitance value (12.5pF). Changed register name at location 0x38 from QUANT_V to QUANT_I. Removed non lead-free packages from Ordering Information. Updated Teridian street address. Added text at explanation of bits 14-12 of the STATUS register stating that these bits are also set when the current is below the threshold defined by bits 15-0 of the START_THRESHLD register. Added at explanation of START_THRESHLD : "Elements with VRMS< V_START will not set the creep bits in the STATUS register" and "Elements with ISQSUM< I_START will set the creep bits in the STATUS register". Added value for RJA in Electrical Specification.
Rev. 1.2
March 15, 2007
Rev. 1.3
August 17, 2007
Rev. 1.4
March 5, 2008
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(c) 2005-2008 TERIDIAN Semiconductor Corporation
V1.4
71M6515H Energy Meter IC
DATA SHEET
MARCH 2008
Final Data Sheet: This Final Data Sheet is proprietary to TERIDIAN Semiconductor Corporation (TSC) and sets forth design goals for the described product. The data sheet is subject to change. TSC assumes no obligation regarding future manufacture, unless agreed to in writing. If and when manufactured and sold, this product is sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement and limitation of liability. TERIDIAN Semiconductor Corporation (TSC) reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that a data sheet is current before placing orders. TSC assumes no liability for applications assistance.
TERIDIAN Semiconductor Corp., 6440 Oak Canyon, Suite 100, Irvine, CA 92618 TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com 3/13/2008
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